hackage.haskell.org : hsverilog
Synthesizable Verilog DSL supporting for multiple clock and reset
Registry
- JSON
purl: pkg:hackage/hsverilog
Keywords:
bsd3
, hardware
, library
, Propose Tags
License: BSD-3-Clause
Latest release: over 10 years ago
First release: over 10 years ago
Downloads: 1,201 total
Last synced: 28 days ago
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