hackage.haskell.org : sv2v
A tool for coverting SystemVerilog to Verilog. Originally forked from the Verilog parser found at https://github.com/tomahawkins/verilog
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purl: pkg:hackage/sv2v
Keywords:
bsd3
, development
, embedded
, hardware
, language
, program
, Propose Tags
, conversion
, systemverilog
, verilog
, yosys
License: BSD-1-Clause
Latest release: 4 months ago
First release: almost 4 years ago
Downloads: 631 total
Stars: 638 on GitHub
Forks: 59 on GitHub
Total Commits: 929
Committers: 10
Average commits per author: 92.9
Development Distribution Score (DDS): 0.012
More commit stats: commits.ecosyste.ms
See more repository details: repos.ecosyste.ms
Last synced: 4 days ago