SystemVerilog 40 Verilog 35 Python 18 HDL 11 VHDL 11 FPGA 10 ASIC 5 Coverage 5 EDA 5 RTL Design 4 Code Generation 4 Hardware Description Language 4 Synthesizable 4 Verilog HDL 4 Functional Verification 3 PSS 3 cocotb 2 Vivado 2 Xilinx 2 python 2 testbench 2 simulation 2 verification 2 Software Generation 2 Register Synthesis 2 Register Addressing 2 Memory 2 Hierarchical Register Description 2 Hardware Design 2 Firmware Generation 2 Electronic Systems 2 Electronic Design Automation 2 Documentation Generation 2 Co-simulation 2 Control and Status Registers 2 Bus Interface 2 Genetic Algorithm 1 crude 1 Design Space 1 TCL 1 eia 1 swaps 1 risk-management 1 risk 1 oil-and-gas 1 oil 1 nymex 1 morningstar 1 finance 1 GoogleTest 1 xsim 1 xsi 1 vivado 1 xilinx 1 Verilator 1 accellera-ucis 1 coverage-database 1 functional-coverage 1 ucis 1 IP 1 test 1 parser 1 circuit 1 system 1 design 1 UVM 1 parse 1 documentation 1 NaturalDocs 1 SystemRDL 1 hdl 1 fusesoc 1 fpga 1 Questa 1 GHDL 1 OSVVM 1 UVVM 1 FuseSoc 1 format 1 validate 1 JIT 1 commodities 1 cme 1 Products 1 Refined Products 1 Refinery 1 Oil 1 Crude 1 Trading 1 Tools 1 Risk 1 CocoTB 1 System 1 symbol 1 symbolator 1 sphinx 1 hdlparse 1