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pypi.org "veriloga" keyword

vagen 0.1.0

Generates verilogA testbench for verification of analog IPs (VLSI design)
2 versions - Latest release: about 2 months ago - 1 dependent repositories - 35 downloads last month - 1 stars on GitHub - 1 maintainer

Related Keywords

cadence 1 cadence-virtuoso 1 generator 1 simulation 1 testbench 1 testbench-generator 1 verilog-a 1 verilog-ams 1 waveform 1 waveform-generator 1