Ecosyste.ms: Packages
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spack.io : verilator
Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Please do not download this program if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator or Verilog compiler for a little project! (Try Icarus instead.) However, if you are looking for a path to migrate synthesizable Verilog to C++ or SystemC, and writing just a touch of C code and Makefiles doesn't scare you off, this is the free Verilog compiler for you. Verilator supports the synthesis subset of Verilog, plus initial statements, proper blocking/non-blocking assignments, functions, tasks, multi-dimensional arrays, and signed numbers. It also supports very simple forms of SystemVerilog assertions and coverage analysis. Verilator supports the more important Verilog 2005 constructs, and some SystemVerilog features, with additional constructs being added as users request them. Verilator has been used to simulate many very large multi-million gate designs with thousands of modules.
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purl: pkg:spack/verilator
License: Other
Latest release: about 2 years ago
First release: about 2 years ago
Last synced: 23 days ago