proxy.golang.org : github.com/freechipsproject/chisel3
Chisel: A Modern Hardware Design Language
Registry
-
Source
- Documentation
- JSON
purl: pkg:golang/github.com/freechipsproject/chisel3
Keywords:
chip-generator
, chisel
, chisel3
, firrtl
, rtl
, scala
, verilog
License: Apache-2.0
Latest release: about 2 months ago
First release: 5 months ago
Stars: 4,231 on GitHub
Forks: 621 on GitHub
Total Commits: 5473
Committers: 205
Average commits per author: 26.698
Development Distribution Score (DDS): 0.852
More commit stats: commits.ecosyste.ms
See more repository details: repos.ecosyste.ms
Last synced: 13 days ago