An open API service providing package, version and dependency metadata of many open source software ecosystems and registries.

proxy.golang.org "verilog" keyword

View the packages on the proxy.golang.org package registry that are tagged with the "verilog" keyword.

Top 5.8% on proxy.golang.org
github.com/damofthemoon/svut v1.10.0
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
33 versions - Latest release: 12 months ago - 61 stars on GitHub
Top 8.6% on proxy.golang.org
github.com/google/xls v0.0.0
XLS: Accelerated HW Synthesis
347 versions - Latest release: over 1 year ago - 1,355 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/veryl-lang/veryl v0.16.4 💰
Veryl: A Modern Hardware Description Language
57 versions - Latest release: 24 days ago - 800 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/FPGAwars/apio v6.0.0+incompatible
:seedling: Open source ecosystem for open FPGA boards
28 versions - Latest release: almost 5 years ago - 893 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/fpgawars/apio v6.0.0+incompatible
:seedling: Open source ecosystem for open FPGA boards
28 versions - Latest release: almost 5 years ago - 893 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/olofk/edalize v0.6.2
An abstraction library for interfacing EDA tools
26 versions - Latest release: 8 days ago - 708 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/SystemRDL/PeakRDL v1.4.0
Control and status register code generator toolchain
16 versions - Latest release: 4 months ago - 145 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/systemrdl/peakrdl v1.4.0
Control and status register code generator toolchain
16 versions - Latest release: 4 months ago - 145 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/clash-lang/clash-compiler v1.8.2
Haskell to VHDL/Verilog/SystemVerilog compiler
57 versions - Latest release: 9 months ago - 1,543 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/cocotb/cocotb v2.0.0+incompatible
cocotb: Python-based chip (RTL) verification
20 versions - Latest release: 20 days ago - 2,085 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/cocotb/cocotb-bus v0.2.1
Pre-packaged testbenching tools and reusable bus interfaces for cocotb
4 versions - Latest release: over 3 years ago - 66 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/the-openroad-project/openroad v0.9.0-beta
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad...
1 version - Latest release: about 5 years ago - 2,180 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/The-OpenROAD-Project/OpenROAD v0.9.0-beta
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad...
1 version - Latest release: about 5 years ago - 2,167 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/dalance/svls v0.2.13 💰
SystemVerilog language server
43 versions - Latest release: 21 days ago - 535 stars on GitHub
Top 8.2% on proxy.golang.org
gitlab.com/tymonx/xlogic-toolchain v0.0.0-20201101210813-670eaf598ed9
Toolchain for simulating and building FPGA projects.
1 version - Latest release: almost 5 years ago - 3 stars on GitLab.com
Top 6.7% on proxy.golang.org
github.com/SpinalHDL/SpinalHDL v1.13.0 💰
Scala based HDL
98 versions - Latest release: 22 days ago - 1,854 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/spinalhdl/spinalhdl v1.13.0 💰
Scala based HDL
98 versions - Latest release: 22 days ago - 1,854 stars on GitHub
Top 5.7% on proxy.golang.org
github.com/platformio/platform-lattice_ice40 v1.3.0
Lattice iCE40: development platform for PlatformIO
9 versions - Latest release: over 3 years ago - 40 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/chipsalliance/chisel v7.1.0+incompatible
Chisel: A Modern Hardware Design Language
87 versions - Latest release: 10 days ago - 4,408 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/mshr-h/vscode-verilog-hdl-support v1.16.1 💰
HDL support for VS Code
58 versions - Latest release: about 2 months ago - 336 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/dpretet/axi-crossbar v1.1.1 💰
An AXI4 crossbar implementation in SystemVerilog
11 versions - Latest release: about 1 month ago - 169 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/siliconcompiler/siliconcompiler v0.34.3
Modular hardware build system
108 versions - Latest release: about 2 months ago - 1,088 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/dalance/sv-parser v0.13.3 💰
SystemVerilog parser library fully compliant with IEEE 1800-2017
57 versions - Latest release: almost 2 years ago - 449 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/reds-heig/logisim-evolution v4.0.0+incompatible
Digital logic design tool and simulator
31 versions - Latest release: 25 days ago - 5,617 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/sgherbst/pysvinst v0.1.9
Python library for parsing module definitions and instantiations from SystemVerilog files
18 versions - Latest release: over 4 years ago - 13 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/cambridgehackers/connectal v18.12.1+incompatible
Connectal is a framework for software-driven hardware development.
27 versions - Latest release: almost 7 years ago - 153 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/ucb-bar/chisel3 v7.0.0+incompatible
Chisel: A Modern Hardware Design Language
86 versions - Latest release: about 1 month ago - 4,238 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/freand76/digsim v0.12.0
An interactive digital logic simulator with verilog support (Yosys)
14 versions - Latest release: 11 days ago - 24 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/freechipsproject/chisel3 v7.0.0+incompatible
Chisel: A Modern Hardware Design Language
86 versions - Latest release: about 1 month ago - 4,231 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/FPGAwars/icestudio v0.9.0
:snowflake: Visual editor for open FPGA boards
21 versions - Latest release: over 3 years ago - 1,803 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/TerosTechnology/vscode-terosHDL v8.0.3+incompatible
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
28 versions - Latest release: about 1 month ago - 646 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/terostechnology/vscode-teroshdl v8.0.3+incompatible
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
28 versions - Latest release: about 1 month ago - 646 stars on GitHub
Top 9.8% on proxy.golang.org
github.com/rj45/rj32/emurj v0.0.0-20220924211506-cf2a2005fb55
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
1 version - Latest release: about 3 years ago - 57 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/dalance/veryl v0.16.4 💰
Veryl: A Modern Hardware Description Language
57 versions - Latest release: 24 days ago - 397 stars on GitHub
Top 6.3% on proxy.golang.org
github.com/tree-sitter/tree-sitter-verilog v1.0.3 💰
SystemVerilog grammar for tree-sitter
3 versions - Latest release: 11 months ago - 108 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/fpgawars/icestudio v0.9.0
:snowflake: Visual editor for open FPGA boards
21 versions - Latest release: over 3 years ago - 1,803 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/ovh/sv2chisel v0.5.0
(System)Verilog to Chisel translator
3 versions - Latest release: over 3 years ago - 112 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/chipsalliance/chisel3 v7.0.0+incompatible
Chisel: A Modern Hardware Design Language
86 versions - Latest release: about 1 month ago - 4,231 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/rggen/rggen-verilog v0.13.2
Verilog writer plugin for RgGen
20 versions - Latest release: 2 months ago - 8 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/drom/reqack v1.3.1
🔁 elastic circuit toolchain
33 versions - Latest release: over 7 years ago - 30 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/hep-soc/socmake v0.3.1
CMake based hardware build system
47 versions - Latest release: 4 months ago - 31 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/HEP-SoC/SoCMake v0.3.1
CMake based hardware build system
47 versions - Latest release: 4 months ago - 31 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/esynr3z/corsair v1.0.4
Control and Status Register map generator for HDL projects
8 versions - Latest release: over 2 years ago - 117 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/sgherbst/svreal v0.2.7
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point for...
16 versions - Latest release: almost 5 years ago - 44 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/potentialventures/cocotb v2.0.0+incompatible
cocotb: Python-based chip (RTL) verification
20 versions - Latest release: 20 days ago - 1,940 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/bensampson5/libsv v0.2.1
An open source, parameterized SystemVerilog digital hardware IP library
2 versions - Latest release: over 3 years ago - 29 stars on GitHub
Top 6.4% on proxy.golang.org
github.com/dalance/svlint v0.9.4 💰
SystemVerilog linter
64 versions - Latest release: 21 days ago - 357 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/zachjs/sv2v v0.0.13
SystemVerilog to Verilog conversion
14 versions - Latest release: 7 months ago - 664 stars on GitHub
Top 4.4% on proxy.golang.org
github.com/Zachjs/sv2v v0.0.13
SystemVerilog to Verilog conversion
14 versions - Latest release: 7 months ago - 664 stars on GitHub
Top 4.4% on proxy.golang.org
github.com/ZachJS/sv2v v0.0.13
SystemVerilog to Verilog conversion
14 versions - Latest release: 7 months ago - 664 stars on GitHub
Top 9.0% on proxy.golang.org
github.com/open-sdr/openwifi v1.5.0
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
6 versions - Latest release: about 2 months ago - 4,320 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/logisim-evolution/logisim-evolution v4.0.0+incompatible
Digital logic design tool and simulator
31 versions - Latest release: 25 days ago - 6,105 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/platformio/platformio-atom-ide v2.7.2+incompatible 💰
PlatformIO IDE for Atom: The next generation integrated development environment for IoT
82 versions - Latest release: about 5 years ago - 476 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/rggen/rggen v0.35.2 💰
Code generation tool for control and status registers
49 versions - Latest release: 2 months ago - 421 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/xtofalex/naja v0.2.10
Structural Netlist API (and more) for EDA post synthesis flow development
29 versions - Latest release: 29 days ago - 100 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/dpretet/async_fifo v1.3.1
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
6 versions - Latest release: over 1 year ago - 325 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/SpinalHDL/SpinalCrypto v1.1.0
SpinalHDL - Cryptography libraries
2 versions - Latest release: about 6 years ago - 56 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/degatecommunity/degate v2.0.0+incompatible 💰
A modern and open-source cross-platform software for chips reverse engineering.
9 versions - Latest release: over 4 years ago - 264 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/jameshanlon/netlist-paths v0.5.0
A library and command-line tool for querying a Verilog netlist.
6 versions - Latest release: over 3 years ago - 26 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/DegateCommunity/Degate v2.0.0+incompatible 💰
A modern and open-source cross-platform software for chips reverse engineering.
9 versions - Latest release: over 4 years ago - 264 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/sgherbst/svinst v0.1.6
Determines the modules declared and instantiated in a SystemVerilog file
16 versions - Latest release: over 4 years ago - 47 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/spinalhdl/spinalcrypto v1.1.0
SpinalHDL - Cryptography libraries
2 versions - Latest release: about 6 years ago - 56 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/esonghori/tinygarble v2.0.1+incompatible
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
6 versions - Latest release: over 9 years ago - 120 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/esonghori/TinyGarble v2.0.1+incompatible
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits
6 versions - Latest release: over 9 years ago - 120 stars on GitHub
Top 9.5% on proxy.golang.org
github.com/rj45/rj32/tilemap
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.
Latest release: about 1 month ago - 68 stars on GitHub