proxy.golang.org "verilog" keyword
View the packages on the proxy.golang.org package registry that are tagged with the "verilog" keyword.
Top 5.8% on proxy.golang.org
33 versions - Latest release: 12 months ago - 61 stars on GitHub
github.com/damofthemoon/svut v1.10.0
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!33 versions - Latest release: 12 months ago - 61 stars on GitHub
Top 8.6% on proxy.golang.org
347 versions - Latest release: over 1 year ago - 1,355 stars on GitHub
github.com/google/xls v0.0.0
XLS: Accelerated HW Synthesis347 versions - Latest release: over 1 year ago - 1,355 stars on GitHub
Top 5.6% on proxy.golang.org
57 versions - Latest release: 24 days ago - 800 stars on GitHub
github.com/veryl-lang/veryl v0.16.4 💰
Veryl: A Modern Hardware Description Language57 versions - Latest release: 24 days ago - 800 stars on GitHub
Top 6.7% on proxy.golang.org
28 versions - Latest release: almost 5 years ago - 893 stars on GitHub
github.com/FPGAwars/apio v6.0.0+incompatible
:seedling: Open source ecosystem for open FPGA boards28 versions - Latest release: almost 5 years ago - 893 stars on GitHub
Top 6.7% on proxy.golang.org
28 versions - Latest release: almost 5 years ago - 893 stars on GitHub
github.com/fpgawars/apio v6.0.0+incompatible
:seedling: Open source ecosystem for open FPGA boards28 versions - Latest release: almost 5 years ago - 893 stars on GitHub
Top 5.8% on proxy.golang.org
26 versions - Latest release: 8 days ago - 708 stars on GitHub
github.com/olofk/edalize v0.6.2
An abstraction library for interfacing EDA tools26 versions - Latest release: 8 days ago - 708 stars on GitHub
Top 5.8% on proxy.golang.org
16 versions - Latest release: 4 months ago - 145 stars on GitHub
github.com/SystemRDL/PeakRDL v1.4.0
Control and status register code generator toolchain16 versions - Latest release: 4 months ago - 145 stars on GitHub
Top 5.8% on proxy.golang.org
16 versions - Latest release: 4 months ago - 145 stars on GitHub
github.com/systemrdl/peakrdl v1.4.0
Control and status register code generator toolchain16 versions - Latest release: 4 months ago - 145 stars on GitHub
Top 5.8% on proxy.golang.org
57 versions - Latest release: 9 months ago - 1,543 stars on GitHub
github.com/clash-lang/clash-compiler v1.8.2
Haskell to VHDL/Verilog/SystemVerilog compiler57 versions - Latest release: 9 months ago - 1,543 stars on GitHub
Top 5.8% on proxy.golang.org
20 versions - Latest release: 20 days ago - 2,085 stars on GitHub
github.com/cocotb/cocotb v2.0.0+incompatible
cocotb: Python-based chip (RTL) verification20 versions - Latest release: 20 days ago - 2,085 stars on GitHub
Top 5.8% on proxy.golang.org
4 versions - Latest release: over 3 years ago - 66 stars on GitHub
github.com/cocotb/cocotb-bus v0.2.1
Pre-packaged testbenching tools and reusable bus interfaces for cocotb4 versions - Latest release: over 3 years ago - 66 stars on GitHub
Top 5.6% on proxy.golang.org
1 version - Latest release: about 5 years ago - 2,180 stars on GitHub
github.com/the-openroad-project/openroad v0.9.0-beta
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad...1 version - Latest release: about 5 years ago - 2,180 stars on GitHub
Top 5.6% on proxy.golang.org
1 version - Latest release: about 5 years ago - 2,167 stars on GitHub
github.com/The-OpenROAD-Project/OpenROAD v0.9.0-beta
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad...1 version - Latest release: about 5 years ago - 2,167 stars on GitHub
Top 6.7% on proxy.golang.org
43 versions - Latest release: 21 days ago - 535 stars on GitHub
github.com/dalance/svls v0.2.13 💰
SystemVerilog language server43 versions - Latest release: 21 days ago - 535 stars on GitHub
Top 8.2% on proxy.golang.org
1 version - Latest release: almost 5 years ago - 3 stars on GitLab.com
gitlab.com/tymonx/xlogic-toolchain v0.0.0-20201101210813-670eaf598ed9
Toolchain for simulating and building FPGA projects.1 version - Latest release: almost 5 years ago - 3 stars on GitLab.com
Top 6.7% on proxy.golang.org
98 versions - Latest release: 22 days ago - 1,854 stars on GitHub
github.com/SpinalHDL/SpinalHDL v1.13.0 💰
Scala based HDL98 versions - Latest release: 22 days ago - 1,854 stars on GitHub
Top 6.7% on proxy.golang.org
98 versions - Latest release: 22 days ago - 1,854 stars on GitHub
github.com/spinalhdl/spinalhdl v1.13.0 💰
Scala based HDL98 versions - Latest release: 22 days ago - 1,854 stars on GitHub
Top 5.7% on proxy.golang.org
9 versions - Latest release: over 3 years ago - 40 stars on GitHub
github.com/platformio/platform-lattice_ice40 v1.3.0
Lattice iCE40: development platform for PlatformIO9 versions - Latest release: over 3 years ago - 40 stars on GitHub
Top 6.7% on proxy.golang.org
87 versions - Latest release: 10 days ago - 4,408 stars on GitHub
github.com/chipsalliance/chisel v7.1.0+incompatible
Chisel: A Modern Hardware Design Language87 versions - Latest release: 10 days ago - 4,408 stars on GitHub
Top 6.7% on proxy.golang.org
58 versions - Latest release: about 2 months ago - 336 stars on GitHub
github.com/mshr-h/vscode-verilog-hdl-support v1.16.1 💰
HDL support for VS Code58 versions - Latest release: about 2 months ago - 336 stars on GitHub
Top 5.6% on proxy.golang.org
11 versions - Latest release: about 1 month ago - 169 stars on GitHub
github.com/dpretet/axi-crossbar v1.1.1 💰
An AXI4 crossbar implementation in SystemVerilog11 versions - Latest release: about 1 month ago - 169 stars on GitHub
Top 5.8% on proxy.golang.org
108 versions - Latest release: about 2 months ago - 1,088 stars on GitHub
github.com/siliconcompiler/siliconcompiler v0.34.3
Modular hardware build system108 versions - Latest release: about 2 months ago - 1,088 stars on GitHub
Top 6.7% on proxy.golang.org
57 versions - Latest release: almost 2 years ago - 449 stars on GitHub
github.com/dalance/sv-parser v0.13.3 💰
SystemVerilog parser library fully compliant with IEEE 1800-201757 versions - Latest release: almost 2 years ago - 449 stars on GitHub
Top 5.8% on proxy.golang.org
31 versions - Latest release: 25 days ago - 5,617 stars on GitHub
github.com/reds-heig/logisim-evolution v4.0.0+incompatible
Digital logic design tool and simulator31 versions - Latest release: 25 days ago - 5,617 stars on GitHub
Top 5.8% on proxy.golang.org
18 versions - Latest release: over 4 years ago - 13 stars on GitHub
github.com/sgherbst/pysvinst v0.1.9
Python library for parsing module definitions and instantiations from SystemVerilog files18 versions - Latest release: over 4 years ago - 13 stars on GitHub
Top 5.8% on proxy.golang.org
27 versions - Latest release: almost 7 years ago - 153 stars on GitHub
github.com/cambridgehackers/connectal v18.12.1+incompatible
Connectal is a framework for software-driven hardware development.27 versions - Latest release: almost 7 years ago - 153 stars on GitHub
Top 5.8% on proxy.golang.org
86 versions - Latest release: about 1 month ago - 4,238 stars on GitHub
github.com/ucb-bar/chisel3 v7.0.0+incompatible
Chisel: A Modern Hardware Design Language86 versions - Latest release: about 1 month ago - 4,238 stars on GitHub
Top 5.6% on proxy.golang.org
14 versions - Latest release: 11 days ago - 24 stars on GitHub
github.com/freand76/digsim v0.12.0
An interactive digital logic simulator with verilog support (Yosys)14 versions - Latest release: 11 days ago - 24 stars on GitHub
Top 5.8% on proxy.golang.org
86 versions - Latest release: about 1 month ago - 4,231 stars on GitHub
github.com/freechipsproject/chisel3 v7.0.0+incompatible
Chisel: A Modern Hardware Design Language86 versions - Latest release: about 1 month ago - 4,231 stars on GitHub
Top 5.8% on proxy.golang.org
21 versions - Latest release: over 3 years ago - 1,803 stars on GitHub
github.com/FPGAwars/icestudio v0.9.0
:snowflake: Visual editor for open FPGA boards21 versions - Latest release: over 3 years ago - 1,803 stars on GitHub
Top 5.6% on proxy.golang.org
28 versions - Latest release: about 1 month ago - 646 stars on GitHub
github.com/TerosTechnology/vscode-terosHDL v8.0.3+incompatible
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!28 versions - Latest release: about 1 month ago - 646 stars on GitHub
Top 5.6% on proxy.golang.org
28 versions - Latest release: about 1 month ago - 646 stars on GitHub
github.com/terostechnology/vscode-teroshdl v8.0.3+incompatible
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!28 versions - Latest release: about 1 month ago - 646 stars on GitHub
Top 9.8% on proxy.golang.org
1 version - Latest release: about 3 years ago - 57 stars on GitHub
github.com/rj45/rj32/emurj v0.0.0-20220924211506-cf2a2005fb55
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.1 version - Latest release: about 3 years ago - 57 stars on GitHub
Top 6.7% on proxy.golang.org
57 versions - Latest release: 24 days ago - 397 stars on GitHub
github.com/dalance/veryl v0.16.4 💰
Veryl: A Modern Hardware Description Language57 versions - Latest release: 24 days ago - 397 stars on GitHub
Top 6.3% on proxy.golang.org
3 versions - Latest release: 11 months ago - 108 stars on GitHub
github.com/tree-sitter/tree-sitter-verilog v1.0.3 💰
SystemVerilog grammar for tree-sitter3 versions - Latest release: 11 months ago - 108 stars on GitHub
Top 5.8% on proxy.golang.org
21 versions - Latest release: over 3 years ago - 1,803 stars on GitHub
github.com/fpgawars/icestudio v0.9.0
:snowflake: Visual editor for open FPGA boards21 versions - Latest release: over 3 years ago - 1,803 stars on GitHub
Top 5.8% on proxy.golang.org
3 versions - Latest release: over 3 years ago - 112 stars on GitHub
github.com/ovh/sv2chisel v0.5.0
(System)Verilog to Chisel translator3 versions - Latest release: over 3 years ago - 112 stars on GitHub
Top 5.8% on proxy.golang.org
86 versions - Latest release: about 1 month ago - 4,231 stars on GitHub
github.com/chipsalliance/chisel3 v7.0.0+incompatible
Chisel: A Modern Hardware Design Language86 versions - Latest release: about 1 month ago - 4,231 stars on GitHub
Top 5.8% on proxy.golang.org
20 versions - Latest release: 2 months ago - 8 stars on GitHub
github.com/rggen/rggen-verilog v0.13.2
Verilog writer plugin for RgGen20 versions - Latest release: 2 months ago - 8 stars on GitHub
Top 5.8% on proxy.golang.org
33 versions - Latest release: over 7 years ago - 30 stars on GitHub
github.com/drom/reqack v1.3.1
🔁 elastic circuit toolchain33 versions - Latest release: over 7 years ago - 30 stars on GitHub
Top 5.6% on proxy.golang.org
47 versions - Latest release: 4 months ago - 31 stars on GitHub
github.com/hep-soc/socmake v0.3.1
CMake based hardware build system47 versions - Latest release: 4 months ago - 31 stars on GitHub
Top 5.6% on proxy.golang.org
47 versions - Latest release: 4 months ago - 31 stars on GitHub
github.com/HEP-SoC/SoCMake v0.3.1
CMake based hardware build system47 versions - Latest release: 4 months ago - 31 stars on GitHub
Top 5.6% on proxy.golang.org
8 versions - Latest release: over 2 years ago - 117 stars on GitHub
github.com/esynr3z/corsair v1.0.4
Control and Status Register map generator for HDL projects8 versions - Latest release: over 2 years ago - 117 stars on GitHub
Top 5.8% on proxy.golang.org
16 versions - Latest release: almost 5 years ago - 44 stars on GitHub
github.com/sgherbst/svreal v0.2.7
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point for...16 versions - Latest release: almost 5 years ago - 44 stars on GitHub
Top 5.8% on proxy.golang.org
20 versions - Latest release: 20 days ago - 1,940 stars on GitHub
github.com/potentialventures/cocotb v2.0.0+incompatible
cocotb: Python-based chip (RTL) verification20 versions - Latest release: 20 days ago - 1,940 stars on GitHub
Top 5.6% on proxy.golang.org
2 versions - Latest release: over 3 years ago - 29 stars on GitHub
github.com/bensampson5/libsv v0.2.1
An open source, parameterized SystemVerilog digital hardware IP library2 versions - Latest release: over 3 years ago - 29 stars on GitHub
Top 6.4% on proxy.golang.org
64 versions - Latest release: 21 days ago - 357 stars on GitHub
github.com/dalance/svlint v0.9.4 💰
SystemVerilog linter64 versions - Latest release: 21 days ago - 357 stars on GitHub
Top 6.7% on proxy.golang.org
14 versions - Latest release: 7 months ago - 664 stars on GitHub
github.com/zachjs/sv2v v0.0.13
SystemVerilog to Verilog conversion14 versions - Latest release: 7 months ago - 664 stars on GitHub
Top 4.4% on proxy.golang.org
14 versions - Latest release: 7 months ago - 664 stars on GitHub
github.com/Zachjs/sv2v v0.0.13
SystemVerilog to Verilog conversion14 versions - Latest release: 7 months ago - 664 stars on GitHub
Top 4.4% on proxy.golang.org
14 versions - Latest release: 7 months ago - 664 stars on GitHub
github.com/ZachJS/sv2v v0.0.13
SystemVerilog to Verilog conversion14 versions - Latest release: 7 months ago - 664 stars on GitHub
Top 9.0% on proxy.golang.org
6 versions - Latest release: about 2 months ago - 4,320 stars on GitHub
github.com/open-sdr/openwifi v1.5.0
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software6 versions - Latest release: about 2 months ago - 4,320 stars on GitHub
Top 5.8% on proxy.golang.org
31 versions - Latest release: 25 days ago - 6,105 stars on GitHub
github.com/logisim-evolution/logisim-evolution v4.0.0+incompatible
Digital logic design tool and simulator31 versions - Latest release: 25 days ago - 6,105 stars on GitHub
Top 5.6% on proxy.golang.org
82 versions - Latest release: about 5 years ago - 476 stars on GitHub
github.com/platformio/platformio-atom-ide v2.7.2+incompatible 💰
PlatformIO IDE for Atom: The next generation integrated development environment for IoT82 versions - Latest release: about 5 years ago - 476 stars on GitHub
Top 5.8% on proxy.golang.org
49 versions - Latest release: 2 months ago - 421 stars on GitHub
github.com/rggen/rggen v0.35.2 💰
Code generation tool for control and status registers49 versions - Latest release: 2 months ago - 421 stars on GitHub
Top 5.6% on proxy.golang.org
29 versions - Latest release: 29 days ago - 100 stars on GitHub
github.com/xtofalex/naja v0.2.10
Structural Netlist API (and more) for EDA post synthesis flow development29 versions - Latest release: 29 days ago - 100 stars on GitHub
Top 5.6% on proxy.golang.org
6 versions - Latest release: over 1 year ago - 325 stars on GitHub
github.com/dpretet/async_fifo v1.3.1
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog6 versions - Latest release: over 1 year ago - 325 stars on GitHub
Top 5.8% on proxy.golang.org
2 versions - Latest release: about 6 years ago - 56 stars on GitHub
github.com/SpinalHDL/SpinalCrypto v1.1.0
SpinalHDL - Cryptography libraries2 versions - Latest release: about 6 years ago - 56 stars on GitHub
Top 5.8% on proxy.golang.org
9 versions - Latest release: over 4 years ago - 264 stars on GitHub
github.com/degatecommunity/degate v2.0.0+incompatible 💰
A modern and open-source cross-platform software for chips reverse engineering.9 versions - Latest release: over 4 years ago - 264 stars on GitHub
Top 5.6% on proxy.golang.org
6 versions - Latest release: over 3 years ago - 26 stars on GitHub
github.com/jameshanlon/netlist-paths v0.5.0
A library and command-line tool for querying a Verilog netlist.6 versions - Latest release: over 3 years ago - 26 stars on GitHub
Top 5.8% on proxy.golang.org
9 versions - Latest release: over 4 years ago - 264 stars on GitHub
github.com/DegateCommunity/Degate v2.0.0+incompatible 💰
A modern and open-source cross-platform software for chips reverse engineering.9 versions - Latest release: over 4 years ago - 264 stars on GitHub
Top 5.8% on proxy.golang.org
16 versions - Latest release: over 4 years ago - 47 stars on GitHub
github.com/sgherbst/svinst v0.1.6
Determines the modules declared and instantiated in a SystemVerilog file16 versions - Latest release: over 4 years ago - 47 stars on GitHub
Top 5.8% on proxy.golang.org
2 versions - Latest release: about 6 years ago - 56 stars on GitHub
github.com/spinalhdl/spinalcrypto v1.1.0
SpinalHDL - Cryptography libraries2 versions - Latest release: about 6 years ago - 56 stars on GitHub
Top 5.6% on proxy.golang.org
6 versions - Latest release: over 9 years ago - 120 stars on GitHub
github.com/esonghori/tinygarble v2.0.1+incompatible
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits6 versions - Latest release: over 9 years ago - 120 stars on GitHub
Top 5.6% on proxy.golang.org
6 versions - Latest release: over 9 years ago - 120 stars on GitHub
github.com/esonghori/TinyGarble v2.0.1+incompatible
TinyGarble: Logic Synthesis and Sequential Descriptions for Yao's Garbled Circuits6 versions - Latest release: over 9 years ago - 120 stars on GitHub
Top 9.5% on proxy.golang.org
Latest release: about 1 month ago - 68 stars on GitHub
github.com/rj45/rj32/tilemap
A 16-bit RISC CPU with 32 instructions built with Digital for running on an FPGA.Latest release: about 1 month ago - 68 stars on GitHub
Related Keywords
fpga
31
systemverilog
24
vhdl
19
rtl
16
asic
12
eda
9
scala
8
python
8
verilator
7
lattice
7
rust
6
icestorm
6
simulator
6
simulation
6
hdl
5
uvm
5
yosys
5
icarus-verilog
5
chisel
5
cpp
5
package
4
amba
4
parser
4
synthesis
4
hardware
4
hardware-description-language
4
firrtl
4
chisel3
4
chip-generator
4
vivado
3
register-descriptions
3
apb
3
csr
3
conversion
3
processor
3
logic
3
cmake
3
uvm-register-model
3
ide
3
hacktoberfest
3
interface
3
verification
3
axi
3
hls
3
module
2
parsing
2
zynq
2
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2
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2
security-protocol
2
instantiation
2
declaration
2
timing-diagram
2
logisim-evolution
2
logisim
2
education
2
digital-logic-design
2
digital-logic
2
digital-circuits
2
digital-circuit
2
circuits
2
circuit
2
soc
2
asic-design
2
verilog-hdl
2
garbled-circuits
2
circuit-description
2
vlsi
2
security-tools
2
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2
reverse-engineering
2
multi-platform
2
gui
2
cybersecurity
2
cross-platform
2
chips
2
spinalhdl
2
sha
2
md5
2
hmac
2
des
2
cryptography
2
crypto
2
crc
2
aes
2
vhdl-language
2
systemc
2
system-on-chip
2
integrated-circuits
2
build-system
2
build-automation
2
vga
2
dvi
2
cpu
2
javascript
2
icestudio
2
cli
2
iverilog
2
manager
2
platformio
2