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proxy.golang.org : github.com/rggen/rggen-systemverilog
SystemVerilog RTL and UVM RAL model generators for RgGen
Registry
-
Source
- Documentation
- JSON
purl: pkg:golang/github.com/rggen/rggen-systemverilog
Keywords:
ral
, rtl
, systemverilog
, uvm
License: MIT
Latest release: 4 months ago
First release: about 6 years ago
Stars: 14 on GitHub
Forks: 1 on GitHub
Total Commits: 255
Committers: 3
Average commits per author: 85.0
Development Distribution Score (DDS): 0.067
More commit stats: commits.ecosyste.ms
See more repository details: repos.ecosyste.ms
Last synced: 23 days ago