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proxy.golang.org "systemverilog" keyword

View the packages on the proxy.golang.org package registry that are tagged with the "systemverilog" keyword.

Top 5.6% on proxy.golang.org
github.com/jameshanlon/netlist-paths v0.5.0
A library and command-line tool for querying a Verilog netlist.
6 versions - Latest release: almost 4 years ago - 26 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/HEP-SoC/SoCMake v0.3.1
CMake based hardware build system
47 versions - Latest release: 6 months ago - 32 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/hep-soc/socmake v0.3.1
CMake based hardware build system
47 versions - Latest release: 6 months ago - 32 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/SystemRDL/PeakRDL v1.5.0
Control and status register code generator toolchain
17 versions - Latest release: 2 months ago - 145 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/chipsalliance/uhdm v0.9.2
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VP...
1 version - Latest release: about 3 years ago - 229 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/damofthemoon/svut v1.10.0
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
33 versions - Latest release: about 1 year ago - 61 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/veryl-lang/veryl v0.17.1 💰
Veryl: A Modern Hardware Description Language
60 versions - Latest release: 10 days ago - 804 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/mshr-h/vscode-verilog-hdl-support v1.16.1 💰
HDL support for VS Code
58 versions - Latest release: 4 months ago - 340 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/clash-lang/clash-compiler v1.8.4
Haskell to VHDL/Verilog/SystemVerilog compiler
59 versions - Latest release: about 1 month ago - 1,545 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/chipsalliance/UHDM v0.9.2
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VP...
1 version - Latest release: about 3 years ago - 229 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/systemrdl/peakrdl v1.5.0
Control and status register code generator toolchain
17 versions - Latest release: 2 months ago - 145 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/dalance/svls v0.2.14 💰
SystemVerilog language server
44 versions - Latest release: about 1 month ago - 535 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/sgherbst/pysvinst v0.1.9
Python library for parsing module definitions and instantiations from SystemVerilog files
18 versions - Latest release: over 4 years ago - 13 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/terostechnology/vscode-teroshdl v8.0.3+incompatible
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
28 versions - Latest release: 4 months ago - 654 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/intel/rohd-hcl v0.2.1
A hardware component library developed with ROHD.
3 versions - Latest release: 3 months ago - 93 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/TerosTechnology/vscode-terosHDL v8.0.3+incompatible
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
28 versions - Latest release: 4 months ago - 646 stars on GitHub
Top 8.2% on proxy.golang.org
github.com/hdl-util/hdmi v1.2.1 💰
Send video/audio over HDMI on an FPGA
2 versions - Latest release: almost 5 years ago - 1,201 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/dalance/veryl v0.17.0 💰
Veryl: A Modern Hardware Description Language
59 versions - Latest release: about 1 month ago - 397 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/rggen/rggen v0.35.2 💰
Code generation tool for control and status registers
49 versions - Latest release: 5 months ago - 427 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/sgherbst/svreal v0.2.7
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point for...
16 versions - Latest release: about 5 years ago - 44 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/dalance/sv-parser v0.13.4 💰
SystemVerilog parser library fully compliant with IEEE 1800-2017
58 versions - Latest release: about 1 month ago - 451 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/bensampson5/libsv v0.2.1
An open source, parameterized SystemVerilog digital hardware IP library
2 versions - Latest release: almost 4 years ago - 29 stars on GitHub
Top 6.4% on proxy.golang.org
github.com/dalance/svlint v0.9.5 💰
SystemVerilog linter
65 versions - Latest release: about 1 month ago - 357 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/olofk/edalize v0.6.3
An abstraction library for interfacing EDA tools
27 versions - Latest release: about 1 month ago - 708 stars on GitHub
Top 4.4% on proxy.golang.org
github.com/Zachjs/sv2v v0.0.13
SystemVerilog to Verilog conversion
14 versions - Latest release: 9 months ago - 664 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/agalimberti/NoCRouter v0.2.1
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Albert...
1 version - Latest release: over 8 years ago - 125 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/dalance/svlint-action v1.0.2 💰
5 versions - Latest release: almost 6 years ago - 8 stars on GitHub
Top 4.4% on proxy.golang.org
github.com/ZachJS/sv2v v0.0.13
SystemVerilog to Verilog conversion
14 versions - Latest release: 9 months ago - 664 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/zachjs/sv2v v0.0.13
SystemVerilog to Verilog conversion
14 versions - Latest release: 9 months ago - 664 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/agalimberti/nocrouter v0.2.1
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Albert...
1 version - Latest release: over 8 years ago - 125 stars on GitHub
Top 5.6% on proxy.golang.org
github.com/taichi-ishitani/tvip-axi v0.1.1 💰
AMBA AXI VIP
1 version - Latest release: about 7 years ago - 389 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/rggen/rggen-systemverilog v0.35.1
SystemVerilog RTL and UVM RAL model generators for RgGen
36 versions - Latest release: 6 months ago - 14 stars on GitHub
Top 5.8% on proxy.golang.org
github.com/sgherbst/svinst v0.1.6
Determines the modules declared and instantiated in a SystemVerilog file
16 versions - Latest release: over 4 years ago - 47 stars on GitHub
Top 6.7% on proxy.golang.org
github.com/pulp-platform/axi v0.39.5
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance o...
87 versions - Latest release: about 1 year ago - 1,386 stars on GitHub