Top 5.0% downloads on pypi.org
Top 2.4% dependent packages on pypi.org
Top 2.4% dependent repos on pypi.org
Top 4.0% forks on pypi.org
pypi.org : pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator
Registry
-
Source
- Documentation
- JSON
purl: pkg:pypi/pyverilog
Keywords:
Verilog HDL
, Lexer
, Parser
, Dataflow Analyzer
, Control-flow Analyzer
, Code Generator
, Visualizer
, code-generator
, compiler
, control-flow-analyzer
, dataflow-analyzer
, hardware
, parser
, python
, verilog-hdl
License: Apache-2.0
Latest release: over 4 years ago
First release: over 10 years ago
Dependent packages: 3
Dependent repositories: 36
Downloads: 6,586 last month
Stars: 682 on GitHub
Forks: 196 on GitHub
Docker dependents: 0
Docker downloads: 0
Total Commits: 301
Committers: 17
Average commits per author: 17.706
Development Distribution Score (DDS): 0.12
More commit stats: commits.ecosyste.ms
See more repository details: repos.ecosyste.ms
Last synced: 1 day ago
syn-magia 0.3.0
Magia generates Synthesizable SystemVerilog in pythonic syntax8 versions - Latest release: over 1 year ago - 140 downloads last month - 545 stars on GitHub - 1 maintainer