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pypi.org : syn-magia

Magia generates Synthesizable SystemVerilog in pythonic syntax

Registry - Source - Documentation - JSON
purl: pkg:pypi/syn-magia
Keywords: Verilog HDL, SystemVerilog, Synthesizable, RTL, HDL, Hardware Description Language, Code Generation, FPGA, ASIC, EDA, RTL Design
License: MIT-feh
Status: removed
Latest release: 5 months ago
First release: 6 months ago
Downloads: 140 last month
Stars: 545 on GitHub
Forks: 160 on GitHub
Total Commits: 301
Committers: 17
Average commits per author: 17.706
Development Distribution Score (DDS): 0.12
More commit stats: commits.ecosyste.ms
See more repository details: repos.ecosyste.ms
Last synced: 15 days ago

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