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Top 5.0% downloads on pypi.org
Top 2.4% dependent packages on pypi.org
Top 2.4% dependent repos on pypi.org
Top 4.0% forks on pypi.org
pypi.org : pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL: Parser, Dataflow Analyzer, Controlflow Analyzer and Code Generator
Registry
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Source
- Documentation
- JSON
purl: pkg:pypi/pyverilog
Keywords: Verilog HDL, Lexer, Parser, Dataflow Analyzer, Control-flow Analyzer, Code Generator, Visualizer, code-generator, compiler, control-flow-analyzer, dataflow-analyzer, hardware, parser, python, verilog-hdl
License: Apache-2.0
Latest release: over 3 years ago
First release: over 9 years ago
Dependent packages: 3
Dependent repositories: 36
Downloads: 2,351 last month
Stars: 571 on GitHub
Forks: 165 on GitHub
Docker dependents: 0
Docker downloads: 0
Total Commits: 301
Committers: 17
Average commits per author: 17.706
Development Distribution Score (DDS): 0.12
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Last synced: 25 days ago