Ecosyste.ms: Packages

FPGA 20 Verilog 14 SystemVerilog 11 RTL 10 HDL 9 verilog 9 simulation 9 hdl 9 Xilinx 7 rtl 7 vhdl 7 Altera 6 synthesis 6 fpga 5 verification 4 python 4 eda 4 EDA 4 Python 4 Synthesis 4 hardware 3 ASIC 3 systemverilog 3 Documentation Generation 2 Co-simulation 2 Control and Status Registers 2 Bus Interface 2 UVM 2 DV 2 C 2 xilinx 2 modelsim 2 ghdl 2 Electronic Design Automation 2 Electronic Systems 2 Firmware Generation 2 Hardware Design 2 Hierarchical Register Description 2 testbench 2 Memory 2 system 2 circuit 2 HLS 2 Software Generation 2 Register Synthesis 2 Register Addressing 2 Python3 2 Hardware 2 design 1 altera 1 Parser 1 network-development-kit 1 liberouter 1 traffic classification 1 machine learning 1 LightGBM 1 wave 1 schematic 1 System 1 HWT 1 documentation 1 sphinx 1 hierarchy 1 parse 1 ip-xact 1 IPXACT 1 pdf 1 md 1 rst 1 html 1 ipxact2vhdl 1 ipxact2systemverilog 1 fusesoc 1 parser 1 test 1 IP 1 development 1 fst 1 vcd 1 myhdl 1 crc32 1 crc-calculation 1 crc-algorithms 1 crc 1 codegenerator 1 MyHDL 1 CRC 1 Electronic 1 Design 1 Automation 1 yosys 1 vivado 1 verilator 1 spyglass 1 riviera-pro 1 lattice 1 icestorm 1 icarus-verilog 1 fossi 1 language-model 1