Ecosyste.ms: Packages

SystemVerilog 39 Verilog 33 Python 17 HDL 10 FPGA 10 VHDL 10 ASIC 5 EDA 5 Synthesizable 4 Hardware Description Language 4 Code Generation 4 Coverage 4 Verilog HDL 4 RTL Design 4 Functional Verification 4 PSS 4 testbench 2 simulation 2 verification 2 Software Generation 2 Register Synthesis 2 python 2 Register Addressing 2 Vivado 2 Xilinx 2 Co-simulation 2 cocotb 2 Control and Status Registers 2 Bus Interface 2 Documentation Generation 2 Electronic Design Automation 2 Electronic Systems 2 Firmware Generation 2 Hardware Design 2 Hierarchical Register Description 2 Memory 2 parser 1 circuit 1 system 1 design 1 swaps 1 risk-management 1 risk 1 oil-and-gas 1 oil 1 TCL 1 UVM 1 accellera-ucis 1 coverage-database 1 functional-coverage 1 ucis 1 xsim 1 xsi 1 vivado 1 xilinx 1 CocoTB 1 IP 1 test 1 Design Space 1 Genetic Algorithm 1 GoogleTest 1 Verilator 1 FuseSoc 1 UVVM 1 OSVVM 1 GHDL 1 Questa 1 fpga 1 fusesoc 1 hdl 1 SystemRDL 1 NaturalDocs 1 documentation 1 Risk 1 Tools 1 Trading 1 Crude 1 Oil 1 Refinery 1 Refined Products 1 Products 1 cme 1 commodities 1 crude 1 eia 1 finance 1 morningstar 1 nymex 1