Ecosyste.ms: Packages
An open API service providing package, version and dependency metadata of many open source software ecosystems and registries.
pypi.org "SystemVerilog" keyword
tblink-rpc-hdl 0.0.0
Provides a TbLink-RPC integration for HDL environments1 version - Latest release: over 1 year ago - 21 downloads last month - 1 maintainer
fsva 1.2.0
fsva (FuseSoc Verification Automation)13 versions - Latest release: almost 2 years ago - 1 dependent repositories - 61 downloads last month - 20 stars on GitHub - 1 maintainer
vsc-solvers 0.0.1.8469955330
Core Verification Stimulus and Coverage library27 versions - Latest release: 2 months ago - 4 dependent packages - 1 dependent repositories - 188 downloads last month - 0 stars on GitHub - 1 maintainer
ipxact2systemverilog 1.0.23
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description25 versions - Latest release: 6 months ago - 1 dependent repositories - 60 downloads last month - 55 stars on GitHub - 1 maintainer
zuspec-sv 0.0.1.8404632036
Core ARL data model library1 version - Latest release: 2 months ago - 11 downloads last month - 1 stars on GitHub - 1 maintainer
zuspec-arl-eval 0.0.1.8427873686
Core ARL data model library33 versions - Latest release: 2 months ago - 5 dependent packages - 1 dependent repositories - 31 downloads last month - 0 stars on GitHub - 1 maintainer
pyapi-compat-if 0.0.1.8428028712
Core Verification Stimulus and Coverage library3 versions - Latest release: 2 months ago - 1 dependent package - 13 downloads last month - 0 stars on GitHub - 1 maintainer
zuspec-be-py 0.0.1.8427800336
Co-specification of hardware, software, design, and test behavior1 version - Latest release: 2 months ago - 1 dependent package - 4 downloads last month - 0 stars on GitHub - 1 maintainer
zuspec-cli 0.0.1.8428737035
Co-specification of hardware, software, design, and test behavior3 versions - Latest release: 2 months ago - 12 downloads last month - 0 stars on GitHub - 1 maintainer
zuspec-py 0.0.1
Co-specification of hardware, software, design, and test behavior6 versions - Latest release: 2 months ago - 4 downloads last month - 0 stars on GitHub - 1 maintainer
mavsec 1.0.0
A tool for the creation of JasperGold SVP principle tcl files.6 versions - Latest release: about 1 month ago - 31 downloads last month - 0 stars on GitHub - 1 maintainer
magia-ip 0.0.1
IP libraries designed with Magia1 version - Latest release: 3 months ago - 9 downloads last month - 0 stars on GitHub - 1 maintainer
libarl 0.0.0
Core ARL model evaluator library13 versions - Latest release: over 1 year ago - 126 downloads last month - 2 stars on GitHub - 1 maintainer
zuspec-be-sw 0.0.1.6503696132
Backend library to generate software output8 versions - Latest release: 8 months ago - 3 dependent packages - 63 downloads last month - 0 stars on GitHub - 1 maintainer
zuspec-arl-dm 0.0.1
Core ARL data model library69 versions - Latest release: 3 months ago - 8 dependent packages - 393 downloads last month - 2 stars on GitHub - 1 maintainer
zuspec-dataclasses 0.0.1.6746116423
Front-end for capturing Action Relation Level models using dataclasses20 versions - Latest release: 7 months ago - 3 dependent packages - 1 dependent repositories - 86 downloads last month - 0 stars on GitHub - 1 maintainer
tblink-rpc-core 0.0.0
Provides the core TbLink-RPC library2 versions - Latest release: over 1 year ago - 45 downloads last month - 2 stars on GitHub - 1 maintainer
pyarl-dataclasses 0.0.1.3519958098
Front-end for capturing Action Relation Level models using dataclasses11 versions - Latest release: over 1 year ago - 50 downloads last month - 0 stars on GitHub - 1 maintainer
uvm-python 0.3.0
uvm-python UVM implementation in Python on top of cocotb6 versions - Latest release: about 1 year ago - 1 dependent repositories - 76 downloads last month - 228 stars on GitHub - 1 maintainer
libsv 0.2.1
An open source, parameterized SystemVerilog hardware IP library2 versions - Latest release: over 2 years ago - 1 dependent repositories - 26 downloads last month - 19 stars on GitHub - 1 maintainer
Top 9.7% on pypi.org
11 versions - Latest release: 7 months ago - 3 dependent packages - 2 dependent repositories - 6.14 thousand downloads last month - 70 stars on GitHub - 1 maintainer
peakrdl 1.1.0
Command-line tool for control/status register automation and code generation.11 versions - Latest release: 7 months ago - 3 dependent packages - 2 dependent repositories - 6.14 thousand downloads last month - 70 stars on GitHub - 1 maintainer
vsc-dm 0.0.1
Core Verification Stimulus and Coverage library63 versions - Latest release: 3 months ago - 6 dependent packages - 1 dependent repositories - 892 downloads last month - 9 stars on GitHub - 1 maintainer
pyucis 0.0.0
PyUCIS provides a Python API for manipulating UCIS coverage data.47 versions - Latest release: about 4 years ago - 1 dependent package - 1 dependent repositories - 2.43 thousand downloads last month - 18 stars on GitHub - 1 maintainer
libvsc 0.0.1.3625801070
Core Verification Stimulus and Coverage library42 versions - Latest release: over 1 year ago - 1 dependent package - 1 dependent repositories - 705 downloads last month - 9 stars on GitHub - 1 maintainer
ivpm 1.0.1
IVPM (IP and Verification Package Manager) is a project-internal package manager.80 versions - Latest release: almost 3 years ago - 1 dependent package - 2 dependent repositories - 1.42 thousand downloads last month - 2 stars on GitHub - 1 maintainer
zuspec 0.0.1.6885112054
Co-specification of hardware, software, design, and test behavior9 versions - Latest release: 7 months ago - 35 downloads last month - 0 stars on GitHub - 1 maintainer
mio-cli 1.3.7
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA...49 versions - Latest release: 17 days ago - 394 downloads last month - 2 stars on GitHub - 1 maintainer
syn-magia 0.3.0 removed
Magia generates Synthesizable SystemVerilog in pythonic syntax8 versions - Latest release: 5 months ago - 140 downloads last month - 545 stars on GitHub - 1 maintainer
peakrdl-sv 0.0.1
A SystemRDL exporter for SystemVerilog1 version - Latest release: 3 months ago - 16 downloads last month - 0 stars on GitHub - 1 maintainer
cocotb-vivado 0.0.3
Limited cocotb/Python interface for Xilinx Vivado Simulator3 versions - Latest release: 4 months ago - 48 downloads last month - 14 stars on GitHub - 1 maintainer
pyhdl-call-if 0.0.1
Python interface for HDL programming interfaces2 versions - Latest release: about 2 months ago - 1 dependent package - 97 downloads last month - 0 stars on GitHub - 1 maintainer
rtlpy 1.0.3
A Library of Python Utilities for RTL Design7 versions - Latest release: 4 months ago - 60 downloads last month - 1 maintainer
pyvsc-dataclasses 0.0.1.8548344824
Front-end for capturing Verification Stimulus and Coverage constructs using dataclasses37 versions - Latest release: about 2 months ago - 6 dependent packages - 1 dependent repositories - 160 downloads last month - 0 stars on GitHub - 1 maintainer
pysvmodel 0.4.1
An abstract SystemVerilog language model (incl. Verilog).8 versions - Latest release: 10 months ago - 1 dependent repositories - 649 downloads last month - 7 stars on GitHub - 2 maintainers
pyhdl-pi-if 0.0.1.8675558542
Python interface for HDL programming interfaces10 versions - Latest release: about 2 months ago - 1 dependent package - 526 downloads last month - 0 stars on GitHub - 1 maintainer
magia-hdl 0.5.0
Magia generates Synthesizable SystemVerilog in pythonic syntax5 versions - Latest release: 3 months ago - 2 dependent packages - 75 downloads last month - 7 stars on GitHub - 1 maintainer
fltools 0.0.1.3357237312
Provides utilities for working with EDA Filelists1 version - Latest release: over 1 year ago - 2 dependent packages - 21 downloads last month - 1 stars on GitHub - 1 maintainer
pyhdl-tlm-if 0.0.1
Python interface for HDL programming interfaces1 version - Latest release: about 2 months ago - 145 downloads last month - 0 stars on GitHub - 1 maintainer
pyhdl-if 0.0.1.9052343530
Python interface for HDL programming interfaces12 versions - Latest release: 21 days ago - 1.9 thousand downloads last month - 0 stars on GitHub - 1 maintainer
magia-flow 0.2.1
Design flow integration and automation with Magia4 versions - Latest release: 20 days ago - 129 downloads last month - 0 stars on GitHub - 1 maintainer
wbfbd 0.0.0
wbfbd1 version - Latest release: over 2 years ago - 1 dependent repositories - 11 downloads last month - 0 stars on GitHub - 1 maintainer
vte 0.0.0
Template-driven content generation script focused on verification14 versions - Latest release: over 4 years ago - 3 dependent repositories - 104 downloads last month - 10 stars on GitHub - 1 maintainer
vlsim 0.0.1
vlsim is a wrapper around Verilator that adds in a simple C++ front-end for clock generation and ...8 versions - Latest release: over 4 years ago - 1 dependent repositories - 224 downloads last month - 6 stars on GitHub - 1 maintainer
pyucis-viewer 0.0.0
PyUCIS Viewer QT5-based viewer for UCIS data.9 versions - Latest release: almost 4 years ago - 1 dependent repositories - 73 downloads last month - 5 stars on GitHub - 1 maintainer
pybfms 0.0.0
PyBFMs provides core libraries and scripts to support Python BFMs driving HDL environments1 version - Latest release: over 4 years ago - 2 dependent repositories - 77 downloads last month - 15 stars on GitHub - 1 maintainer
pybfms-generic-sram 0.0.1.20200226.3
pybfms_generic_sram provides bus functional models for the SRAM protocols1 version - Latest release: over 4 years ago - 1 dependent repositories - 7 downloads last month - 0 stars on GitHub - 1 maintainer
fbdl 0.2.0
Functional Bus Description Language compiler front-end.3 versions - Latest release: over 2 years ago - 1 dependent repositories - 10 downloads last month - 0 stars on GitHub - 1 maintainer
ipxact2sv 1.0.6
Generate SystemVerilog, html, rst, md, pdf, docx, C headers from an IPXACT description8 versions - Latest release: 3 months ago - 26 downloads last month - 0 stars on GitHub - 1 maintainer
sverilogpy 0.0.0a2
A python System Verilog Parser and AST3 versions - Latest release: 5 months ago - 342 downloads last month - 0 stars on GitHub - 1 maintainer
Top 7.7% on pypi.org
22 versions - Latest release: 2 months ago - 1 dependent package - 3 dependent repositories - 8.45 thousand downloads last month - 46 stars on GitHub - 1 maintainer
peakrdl-regblock 0.22.0
Compile SystemRDL into a SystemVerilog control/status register (CSR) block22 versions - Latest release: 2 months ago - 1 dependent package - 3 dependent repositories - 8.45 thousand downloads last month - 46 stars on GitHub - 1 maintainer
hdl-checker 0.7.4
HDL code checker19 versions - Latest release: almost 3 years ago - 2 dependent repositories - 301 downloads last month - 176 stars on GitHub - 1 maintainer
mio-client 1.5.9 removed
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA...64 versions - Latest release: over 1 year ago - 1.33 thousand downloads last month - 1 stars on GitHub
Related Keywords
Verilog
41
RTL
39
Python
17
FPGA
11
VHDL
11
HDL
7
ASIC
6
verilog
6
systemverilog
5
EDA
5
hdl
5
Code Generation
4
RTL Design
4
PSS
4
Functional Verification
4
UVM
4
Coverage
4
tool
4
Hardware Description Language
4
Synthesizable
4
fpga
4
Verilog HDL
4
simulation
4
rtl
3
asic
3
Xilinx
3
CSR
3
python
3
Register Addressing
2
Memory
2
Register Synthesis
2
generator
2
registers
2
compiler
2
PeakRDL
2
Software Generation
2
xilinx
2
cocotb
2
SystemRDL
2
Altera
2
synthesis
2
DV
2
Bus Interface
2
Control and Status Registers
2
Co-simulation
2
systemrdl-compiler
2
Documentation Generation
2
Electronic Design Automation
2
eda
2
csr
2
Electronic Systems
2
Firmware Generation
2
Hardware Design
2
Hierarchical Register Description
2
register abstraction layer
2
verification
2
html
2
rst
2
md
2
pdf
2
IPXACT
2
vhdl
2
system-verilog
1
model
1
edaa
1
mentor-msim
1
modelsim
1
questasim
1
syntax-checker
1
vim
1
vim-ale
1
abstract
1
Abstract
1
Model
1
vivado-simulator
1
Language
1
Python3
1
utilities
1
xilinx-vivado
1
CocoTB
1
LSP
1
language
1
server
1
protocol
1
vimhdl
1
vim-hdl
1
coc-nvim
1
emacs-lsp
1
ghdl
1
hdl-checker
1
linter
1
language-server
1
systemverilog-hdl
1
systemrdl
1
ipxact2sv
1
GoogleTest
1
Verilator
1
lsp-server
1
hardware-designs
1
hardware
1