proxy.golang.org : github.com/dpretet/async_fifo
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Registry
-
Source
- Documentation
- JSON
- codemeta.json
purl: pkg:golang/github.com/dpretet/async_fifo
Keywords:
asic
, asic-design
, async
, cdc
, cross-clock-domain
, fifo
, fifo-cache
, fifo-queue
, fpga
, hdl
, icarus-verilog
, synthesis
, verification
, verilator
, verilog
, verilog-hdl
License: GPL-1.0+
Latest release: over 1 year ago
First release: over 7 years ago
Stars: 325 on GitHub
Forks: 83 on GitHub
See more repository details: repos.ecosyste.ms
Last synced: 10 days ago