proxy.golang.org : github.com/dpretet/axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
Registry
-
Source
- Documentation
- JSON
purl: pkg:golang/github.com/dpretet/axi-crossbar
Keywords:
amba
, arm
, asic
, asic-design
, axi4
, axi4-full
, axi4-lite
, axi4-protocol
, crossbar
, fpga
, fpga-soc
, interconnect
, monodraw
, processor
, riscv
, riscv32
, riscv64
, soc
, verilog
License: MIT
Latest release: 18 days ago
First release: almost 4 years ago
Stars: 169 on GitHub
Forks: 30 on GitHub
See more repository details: repos.ecosyste.ms
Funding links: https://github.com/sponsors/dpretet
Last synced: 18 days ago