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proxy.golang.org : github.com/esynr3z/corsair
Control and Status Register map generator for HDL projects
Registry
-
Source
- Documentation
- JSON
purl: pkg:golang/github.com/esynr3z/corsair
Keywords:
asic
, fpga
, python
, system-verilog
, verilog
License: MIT
Latest release: over 2 years ago
First release: over 4 years ago
Stars: 117 on GitHub
Forks: 40 on GitHub
Total Commits: 236
Committers: 6
Average commits per author: 39.333
Development Distribution Score (DDS): 0.144
More commit stats: commits.ecosyste.ms
See more repository details: repos.ecosyste.ms
Last synced: about 1 month ago
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