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An interactive digital logic simulator with verilog support (Yosys)
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purl: pkg:golang/github.com/freand76/digsim
Keywords:
logic
, python
, rtl
, simulation
, simulator
, vcd
, verilog
, yosys
License: GPL-1.0+
Latest release: 27 days ago
First release: almost 2 years ago
Stars: 24 on GitHub
Forks: 0 on GitHub
See more repository details: repos.ecosyste.ms
Last synced: 27 days ago
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