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pypi.org : msdsl
Library for generating synthesizable mixed-signal models for FPGA emulation
Registry
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Source
- Documentation
- JSON
purl: pkg:pypi/msdsl
Keywords: analog, mixed-signal, mixed signal, behavioral, real number model, real number models, rnm, rnms, model, models, generator, verilog, system-verilog, system verilog, synthesizable, emulation, fpga, ams, analog-circuits, python, real-number-modeling, simulation, synthesis
License: MIT
Latest release: almost 3 years ago
First release: over 4 years ago
Dependent repositories: 2
Downloads: 141 last month
Stars: 33 on GitHub
Forks: 10 on GitHub
Total Commits: 296
Committers: 5
Average commits per author: 59.2
Development Distribution Score (DDS): 0.189
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Last synced: 18 days ago