Ecosyste.ms: Packages

An open API service providing package, version and dependency metadata of many open source software ecosystems and registries.

pypi.org "verilog" keyword

Top 7.9% on pypi.org
vcdvcd 2.3.5 💰
Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line viewer
15 versions - Latest release: 4 months ago - 2 dependent packages - 11 dependent repositories - 2.32 thousand downloads last month - 49 stars on GitHub - 1 maintainer
aide-core 1.0.1000 💰
A professional collaborative platform for embedded development. Cross-platform IDE and Unified De...
3 versions - Latest release: 9 months ago - 31 downloads last month - 7,563 stars on GitHub - 1 maintainer
Top 1.3% on pypi.org
platformio 6.1.15 💰
Your Gateway to Embedded Software Development Excellence. Unlock the true potential of embedded s...
116 versions - Latest release: 20 days ago - 4 dependent packages - 423 dependent repositories - 455 thousand downloads last month - 7,563 stars on GitHub - 1 maintainer
pyslang 5.0.0
Python bindings for slang, a library for compiling SystemVerilog
8 versions - Latest release: 5 months ago - 1 dependent package - 1.49 thousand downloads last month - 540 stars on GitHub - 1 maintainer
pyedaa.projectmodel 0.4.3
An abstract model of EDA tool projects.
7 versions - Latest release: 10 months ago - 642 downloads last month - 10 stars on GitHub - 2 maintainers
Top 9.7% on pypi.org
peakrdl 1.1.0
Command-line tool for control/status register automation and code generation.
11 versions - Latest release: 7 months ago - 3 dependent packages - 2 dependent repositories - 6.08 thousand downloads last month - 67 stars on GitHub - 1 maintainer
hdlconvertor 2.3
VHDL and System Verilog parser written in c++
19 versions - Latest release: almost 3 years ago - 1 dependent package - 1 dependent repositories - 167 downloads last month - 265 stars on GitHub - 1 maintainer
hdlconvertor-binary 2.3
VHDL and System Verilog parser written in c++
1 version - Latest release: 4 months ago - 112 downloads last month - 265 stars on GitHub - 1 maintainer
hdlconvertorast 1.2
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities
12 versions - Latest release: 7 months ago - 1 dependent repositories - 1.02 thousand downloads last month - 26 stars on GitHub - 1 maintainer
Top 3.4% on pypi.org
fusesoc 2.2.1
FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code.
24 versions - Latest release: about 1 year ago - 6 dependent packages - 18 dependent repositories - 3.27 thousand downloads last month - 1,118 stars on GitHub - 2 maintainers
Top 3.5% on pypi.org
edalize 0.5.4
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common ...
25 versions - Latest release: 5 months ago - 4 dependent packages - 16 dependent repositories - 3.76 thousand downloads last month - 587 stars on GitHub - 1 maintainer
dmppl 0.2.0
Dave McEwan's Personal Python Library
1 version - Latest release: almost 4 years ago - 1 dependent repositories - 25 downloads last month - 1 stars on GitHub - 1 maintainer
openlane 2.0.5
An infrastructure for implementing chip design flows
83 versions - Latest release: 1 day ago - 1 dependent package - 1 dependent repositories - 1.19 thousand downloads last month - 1,176 stars on GitHub - 2 maintainers
Top 2.1% on pypi.org
cocotb 1.8.1
cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.
37 versions - Latest release: 7 months ago - 17 dependent packages - 71 dependent repositories - 58.4 thousand downloads last month - 1,615 stars on GitHub - 4 maintainers
tsfpga 12.3.3
A flexible and scalable development platform for modern FPGA projects
30 versions - Latest release: 1 day ago - 1 dependent package - 1 dependent repositories - 978 downloads last month - 6 stars on GitHub - 1 maintainer
crcgen 2.6
CRC algorithm HDL code generator (VHDL, Verilog, MyHDL)
7 versions - Latest release: 7 months ago - 35 downloads last month - 23 stars on GitHub - 1 maintainer
verilog-pad-analyzer 0.0.6
VerilogPADAnalyzer is a Python application designed to analyze and report the
6 versions - Latest release: about 2 months ago - 777 downloads last month - 2 stars on GitHub - 1 maintainer
anyv-registers 0.1.0
A template-based hardware register bank generator
1 version - Latest release: 3 months ago - 8 downloads last month - 0 stars on GitHub - 1 maintainer
pip-hdl 0.3.0
Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Pyth...
3 versions - Latest release: 4 months ago - 27 downloads last month - 4 stars on GitHub - 1 maintainer
digsim-logic-simulator 0.4.0
Interactive Digital Logic Simulator
5 versions - Latest release: about 1 month ago - 103 downloads last month - 9 stars on GitHub - 1 maintainer
cocotbext-ahb 0.2.6
CocotbExt AHB Bus VIP
19 versions - Latest release: 5 months ago - 148 downloads last month - 5 stars on GitHub - 1 maintainer
super-ide 1.5.0
A professional Cross-platform IDE. Cross-platform IDE and Unified Debugger. Static Code Analyzer ...
32 versions - Latest release: 19 days ago - 324 downloads last month - 1 maintainer
litexcnc 1.2.4
Generic CNC firmware and driver for FPGA cards which are supported by LiteX
11 versions - Latest release: 3 months ago - 1 dependent repositories - 106 downloads last month - 49 stars on GitHub - 1 maintainer
Top 7.3% on pypi.org
pymtl3 3.1.16
PyMTL 3 (Mamba): A Python-based hardware generation, simulation, and verification framework
31 versions - Latest release: 6 months ago - 3 dependent repositories - 761 downloads last month - 351 stars on GitHub - 2 maintainers
pueda 0.1.12
Collection of python for micro-Electronic Design Automation
9 versions - Latest release: 3 months ago - 29 downloads last month - 1 stars on GitHub - 1 maintainer
morell-test-attempt-verilog 0.0.2 removed
A Verilog Class
2 versions - Latest release: about 1 year ago - 71 downloads last month - 1 maintainer
morell-verilog-class 0.0.1 removed
A Verilog Class
1 version - Latest release: about 1 year ago - 1 maintainer
hgdb-rtl 0.0.1
Creating HGDB symbol table from RTL
1 version - Latest release: over 1 year ago - 10 downloads last month - 536 stars on GitHub - 1 maintainer
pyipcore 0.4.5
(PyQt5 based) Create "Ipcore" from verilog(Need iverilog). Provide "Param Value" and "Port Contro...
17 versions - Latest release: 2 months ago - 85 downloads last month - 1 maintainer
veriloghex 0.1.2
Loading from and dumping to Verilog Hex files
2 versions - Latest release: over 1 year ago - 1 dependent package - 1 dependent repositories - 21 downloads last month - 0 stars on GitHub - 1 maintainer
wavedisp 1.0.6
Wave file generator for HDL waveform viewers
7 versions - Latest release: about 4 years ago - 1 dependent repositories - 37 downloads last month - 10 stars on GitHub - 1 maintainer
verilog-parser 0.0.1
Parser for structural verilog.
2 versions - Latest release: about 3 years ago - 1 dependent repositories - 98 downloads last month - 2 stars on codeberg.org - 1 maintainer
Top 9.0% on pypi.org
symbolator 1.0.2
HDL symbol generator
3 versions - Latest release: over 6 years ago - 13 dependent repositories - 102 downloads last month - 169 stars on GitHub - 1 maintainer
svreal 0.2.7
Library for working with fixed-point numbers in SystemVerilog
26 versions - Latest release: over 3 years ago - 2 dependent repositories - 88 downloads last month - 40 stars on GitHub - 1 maintainer
svmodule 1.2.0
[System]Verilog Module I/O parser and printer
6 versions - Latest release: almost 3 years ago - 1 dependent repositories - 59 downloads last month - 22 stars on GitHub - 1 maintainer
sphinx-verilog-domain 0.0.2
Verilog Domain for Sphinx
3 versions - Latest release: over 3 years ago - 10 dependent repositories - 225 downloads last month - 21 stars on GitHub - 2 maintainers
sphinxcontrib-verilog-diagrams 0.1.1
Compatibility stub for renamed to sphinxcontrib-hdl-diagrams.
13 versions - Latest release: 8 months ago - 2 dependent repositories - 8 downloads last month - 48 stars on GitHub - 3 maintainers
scratchip 0.3.1
ScratChip is a framework that can help to build your Chisel and Verilog/Systemverilog project eas...
5 versions - Latest release: about 2 years ago - 1 dependent repositories - 33 downloads last month - 1 maintainer
sandpiper-saas 1.0.1
Sandpiper SaaS
5 versions - Latest release: almost 3 years ago - 1 dependent repositories - 576 downloads last month - 5 stars on GitHub - 1 maintainer
recover 0.0.0
An effective Remote Co-Verification (ReCoVer) library of hardware and software co-designs
1 version - Latest release: over 4 years ago - 2 dependent repositories - 17 downloads last month - 0 stars on GitLab.com - 1 maintainer
pynqpandas 0.0.1
Hardware-accelerated Pandas
1 version - Latest release: over 6 years ago - 1 dependent repositories - 7 downloads last month - 0 stars on GitHub - 1 maintainer
pyhgl 0.2.0
a Python-based Hardware Generation Language
4 versions - Latest release: 12 months ago - 1 dependent repositories - 8 downloads last month - 869 stars on GitHub - 1 maintainer
py-hcl 0.1.2
A Hardware Construct Language
4 versions - Latest release: over 4 years ago - 1 dependent repositories - 38 downloads last month - 38 stars on GitHub - 1 maintainer
py4hw 0.0.12
py4hw is a library to model, and simulate digital logic circuits. It promotes the use of structur...
12 versions - Latest release: 7 months ago - 1 dependent repositories - 24 downloads last month - 8 stars on GitHub - 1 maintainer
msdsl 0.3.8
Library for generating synthesizable mixed-signal models for FPGA emulation
42 versions - Latest release: almost 3 years ago - 2 dependent repositories - 141 downloads last month - 33 stars on GitHub - 1 maintainer
logic-toolchain 0.0.2
Wrapper for FPGA toolchain tools
2 versions - Latest release: over 5 years ago - 1 dependent repositories - 91 downloads last month - 0 stars on GitLab.com - 1 maintainer
knitkit 0.1.4
KnitKit is a framework that can help to build project easier.
5 versions - Latest release: over 2 years ago - 1 dependent repositories - 29 downloads last month - 1 maintainer
ipxact2systemverilog 1.0.23
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description
25 versions - Latest release: 6 months ago - 1 dependent repositories - 80 downloads last month - 55 stars on GitHub - 1 maintainer
intoyuniot 3.4.4
An open source tools for IntoYun IoT development. Cross-platform build system and library manager...
5 versions - Latest release: over 6 years ago - 1 dependent repositories - 52 downloads last month - 1 maintainer
hwtlib 2.9
library of hardware components and test for HWToolkit framework (hwt, FPGA devel. tools)
28 versions - Latest release: almost 3 years ago - 1 dependent repositories - 81 downloads last month - 32 stars on GitHub - 1 maintainer
Top 9.5% on pypi.org
hwt 3.8
hdl synthesis toolkit
33 versions - Latest release: almost 3 years ago - 7 dependent repositories - 187 downloads last month - 188 stars on GitHub - 1 maintainer
hcm 0.14
HDL Component Manager
14 versions - Latest release: almost 5 years ago - 1 dependent repositories - 50 downloads last month - 10 stars on GitHub - 1 maintainer
erroranalyzer 2.2.1
ErrorAnalyzer is the EDA tool of choice to understand and find simulation failures faster
3 versions - Latest release: over 2 years ago - 1 dependent repositories - 28 downloads last month - 10 stars on GitHub - 1 maintainer
elfws 0.11.0
EDA Log File Warning Suppressor
13 versions - Latest release: 7 days ago - 1 dependent repositories - 104 downloads last month - 2 stars on GitHub - 1 maintainer
sdf-timing 0.0.post131
Python library for working Standard Delay Format (SDF) Timing Annotation files.
5 versions - Latest release: over 1 year ago - 1 dependent repositories - 50 downloads last month - 27 stars on GitHub - 3 maintainers
design-explorer 0.3
Design Explorer
3 versions - Latest release: almost 6 years ago - 1 dependent repositories - 13 downloads last month - 0 stars on GitHub - 1 maintainer
cosa 0.3.1
CoreIR Symbolic Analyzer
14 versions - Latest release: about 5 years ago - 5 dependent repositories - 48 downloads last month - 60 stars on GitHub - 2 maintainers
corsair 1.0.4
Control and Status Register map generator for FPGA/ASIC projects
8 versions - Latest release: about 1 year ago - 1 dependent repositories - 100 downloads last month - 85 stars on GitHub - 1 maintainer
Top 4.5% on pypi.org
cocotb-bus 0.2.1
Pre-packaged testbenching tools and reusable bus interfaces for cocotb
5 versions - Latest release: over 2 years ago - 7 dependent packages - 21 dependent repositories - 14.3 thousand downloads last month - 46 stars on GitHub - 4 maintainers
chipy 0.1.1
Chipy is a single-file python module for generating digital hardware.
1 version - Latest release: about 6 years ago - 1 dependent repositories - 17 downloads last month - 16 stars on GitHub - 1 maintainer
Top 8.0% on pypi.org
sphinxcontrib-hdl-diagrams 0.0.post160
Generate diagrams from HDL in Sphinx.
9 versions - Latest release: 8 months ago - 1 dependent package - 16 dependent repositories - 253 downloads last month - 48 stars on GitHub - 3 maintainers
wal-lang 0.8.0
Wal - Wavefile Analysis Language
2 versions - Latest release: 4 months ago - 1 dependent repositories - 39 downloads last month - 109 stars on GitHub - 2 maintainers
xeda 0.2.5
Cross EDA Abstraction and Automation
34 versions - Latest release: 10 months ago - 1 dependent repositories - 155 downloads last month - 32 stars on GitHub - 1 maintainer
antlr4-verilog 4.0.0
Generated files from ANTLR4 for Verilog parsing
4 versions - Latest release: almost 2 years ago - 1 dependent repositories - 436 downloads last month - 9 stars on GitHub - 1 maintainer
Top 5.5% on pypi.org
apio 0.9.4
Open source ecosystem for open FPGA boards
132 versions - Latest release: 16 days ago - 8 dependent repositories - 2.68 thousand downloads last month - 755 stars on GitHub - 3 maintainers
svinst 0.1.9
Python library for parsing module definitions and instantiations from SystemVerilog files
37 versions - Latest release: about 3 years ago - 1 dependent repositories - 420 downloads last month - 39 stars on GitHub - 1 maintainer
playhdl 0.2.1
Tool to play with HDL (inspired by EdaPlayground)
3 versions - Latest release: over 1 year ago - 31 downloads last month - 4 stars on GitHub - 1 maintainer
hdl-checker 0.7.4
HDL code checker
19 versions - Latest release: almost 3 years ago - 2 dependent repositories - 301 downloads last month - 176 stars on GitHub - 1 maintainer
ipsocgen 0.1.39
Generic SoC builder in HDL
42 versions - Latest release: 11 months ago - 273 downloads last month - 1 maintainer
svut 1.9.0 💰
SystemVerilog Unit Test (SVUT)
2 versions - Latest release: over 1 year ago - 42 downloads last month - 61 stars on GitHub - 1 maintainer
anasymod 0.4.0
Tool for running mixed-signal emulations on FPGAs
52 versions - Latest release: almost 3 years ago - 1 dependent repositories - 149 downloads last month - 31 stars on GitHub - 1 maintainer
mio-cli 1.3.6
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA...
48 versions - Latest release: 5 months ago - 163 downloads last month - 2 stars on GitHub - 1 maintainer
libsv 0.2.1
An open source, parameterized SystemVerilog hardware IP library
2 versions - Latest release: over 2 years ago - 1 dependent repositories - 17 downloads last month - 19 stars on GitHub - 1 maintainer
mio-client 1.5.9 removed
The Moore.io Command Line Interface (CLI) Client is a toolchain for front-end engineering of FPGA...
64 versions - Latest release: over 1 year ago - 1.33 thousand downloads last month - 1 stars on GitHub