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pypi.org : magia-hdl
Magia generates Synthesizable SystemVerilog in pythonic syntax
Registry
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Source
- Documentation
- JSON
purl: pkg:pypi/magia-hdl
Keywords: Verilog HDL, SystemVerilog, Synthesizable, RTL, HDL, Hardware Description Language, Code Generation, FPGA, ASIC, EDA, RTL Design
License: MIT-feh
Latest release: 4 months ago
First release: 5 months ago
Dependent packages: 2
Downloads: 75 last month
Stars: 7 on GitHub
Forks: 1 on GitHub
See more repository details: repos.ecosyste.ms
Last synced: 29 days ago