proxy.golang.org : github.com/rggen/rggen
Code generation tool for control and status registers
Registry
-
Source
- Documentation
- JSON
- codemeta.json
purl: pkg:golang/github.com/rggen/rggen
Keywords:
amba
, apb
, asic
, axi
, csr
, eda
, fpga
, ral
, register-descriptions
, rtl
, soc
, systemverilog
, uvm
, uvm-ral-model
, uvm-register-model
, verilog
, vhdl
, wiki-documents
, wishbone-bus
License: MIT
Latest release: 4 months ago
First release: over 6 years ago
Stars: 427 on GitHub
Forks: 55 on GitHub
Total Commits: 325
Committers: 4
Average commits per author: 81.25
Development Distribution Score (DDS): 0.043
More commit stats: commits.ecosyste.ms
See more repository details: repos.ecosyste.ms
Funding links: https://github.com/sponsors/taichi-ishitani, https://ko-fi.com/taichi730
Last synced: 13 days ago