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proxy.golang.org : github.com/zachjs/sv2v
SystemVerilog to Verilog conversion
Registry
-
Source
- Documentation
- JSON
purl: pkg:golang/github.com/zachjs/sv2v
Keywords:
conversion
, systemverilog
, verilog
, yosys
License: BSD-3-Clause
Latest release: 7 months ago
First release: over 6 years ago
Stars: 664 on GitHub
Forks: 60 on GitHub
Total Commits: 929
Committers: 10
Average commits per author: 92.9
Development Distribution Score (DDS): 0.012
More commit stats: commits.ecosyste.ms
See more repository details: repos.ecosyste.ms
Last synced: 23 days ago