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pypi.org : magia-hdl
Magia generates Synthesizable SystemVerilog in pythonic syntax
Registry
-
Source
- Documentation
- JSON
purl: pkg:pypi/magia-hdl
Keywords:
Verilog HDL
, SystemVerilog
, Synthesizable
, RTL
, HDL
, Hardware Description Language
, Code Generation
, FPGA
, ASIC
, EDA
, RTL Design
License: MIT-feh
Latest release: over 1 year ago
First release: over 1 year ago
Dependent packages: 2
Downloads: 57 last month
Stars: 10 on GitHub
Forks: 1 on GitHub
See more repository details: repos.ecosyste.ms
Last synced: 17 days ago
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