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pypi.org "Synthesizable" keyword

syn-magia 0.3.0
Magia generates Synthesizable SystemVerilog in pythonic syntax
8 versions - Latest release: almost 3 years ago - 140 downloads last month - 802 stars on GitHub - 1 maintainer
magia-hdl 0.5.0
Magia generates Synthesizable SystemVerilog in pythonic syntax
5 versions - Latest release: over 2 years ago - 2 dependent packages - 87 downloads last month - 10 stars on GitHub - 1 maintainer
magia-flow 0.2.1
Design flow integration and automation with Magia
4 versions - Latest release: over 2 years ago - 34 downloads last month - 0 stars on GitHub - 1 maintainer
magia-ip 0.0.1
IP libraries designed with Magia
1 version - Latest release: over 2 years ago - 15 downloads last month - 0 stars on GitHub - 1 maintainer
Related Keywords
Verilog HDL 4 SystemVerilog 4 RTL 4 HDL 4 Hardware Description Language 4 Code Generation 4 FPGA 4 ASIC 4 EDA 4 RTL Design 4