Ecosyste.ms: Packages

HDL 28 ASIC 22 VHDL 20 fpga 16 hardware 14 Verilog 11 SystemVerilog 11 verilog 11 hdl 11 RTL 10 rtl 9 EDA 9 Verilog HDL 9 design 9 python 8 simulation 8 Xilinx 8 Altera 7 eda 6 synthesis 6 InAccel Coral 5 inaccel 5 vhdl 5 Synthesizable 4 Hardware Description Language 4 Code Generation 4 RTL Design 4 Python 4 Synthesis 4 compiler 4 verification 4 Hardware 3 SystemRDL 3 documentation 3 High-Level Synthesis 3 high-level-synthesis 3 systemverilog 3 circuit 3 C 3 asic 3 sphinx 2 automation 2 Software Generation 2 Register Synthesis 2 Memory 2 myhdl 2 RedPitaya 2 yosys 2 Instrumentation 2 IP-core 2 AMBA AXI4 2 testbench 2 Register Addressing 2 UVM 2 DV 2 Hierarchical Register Description 2 HLS 2 Hardware Design 2 zynq 2 Firmware Generation 2 Simulator 2 Design 2 System 2 system 2 Bus Interface 2 Control and Status Registers 2 Co-simulation 2 Electronic Systems 2 Documentation Generation 2 Electronic Design Automation 2 PeakRDL 2 generator 2 registers 2 systemrdl-compiler 2 register abstraction layer 2 verilog-hdl 2 pyverilog 2 DSP 2 CSR 2 tool 2 hardware design 2 csr 2 FPGA-based Rapid Prototyping 1 Memory System Abstraction 1 fusesoc 1 Questa 1 GHDL 1 OSVVM 1 SDK 1 Cycle-Accurate Simulation 1 JTAG 1 ECP5 1 WiFi 1 FTP 1 FLASH 1 SD 1 nMigen 1 RTLIL 1 sphinx-extension 1 netlistsvg 1