pypi.org "systemverilog-hdl" keyword
View the packages on the pypi.org package registry that are tagged with the "systemverilog-hdl" keyword.
Top 3.2% on pypi.org
92 versions - Latest release: almost 2 years ago - 4 dependent packages - 19 dependent repositories - 16.3 thousand downloads last month - 721 stars on GitHub - 2 maintainers
vunit-hdl 4.7.0
VUnit is an open source unit testing framework for VHDL/SystemVerilog.92 versions - Latest release: almost 2 years ago - 4 dependent packages - 19 dependent repositories - 16.3 thousand downloads last month - 721 stars on GitHub - 2 maintainers
Top 7.7% on pypi.org
24 versions - Latest release: 8 days ago - 1 dependent package - 3 dependent repositories - 52.4 thousand downloads last month - 60 stars on GitHub - 1 maintainer
peakrdl-regblock 1.0.0
Compile SystemRDL into a SystemVerilog control/status register (CSR) block24 versions - Latest release: 8 days ago - 1 dependent package - 3 dependent repositories - 52.4 thousand downloads last month - 60 stars on GitHub - 1 maintainer
Related Keywords
asic
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fpga
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testbench
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unit-testing
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universal-verification-methodology
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verification
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verilog-hdl
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vhdl
1
SystemRDL
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PeakRDL
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CSR
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compiler
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tool
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registers
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generator
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Verilog
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SystemVerilog
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register abstraction layer
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FPGA
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ASIC
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csr
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systemrdl
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systemrdl-compiler
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systemverilog
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