Ecosyste.ms: Packages

An open API service providing package, version and dependency metadata of many open source software ecosystems and registries.

pypi.org "asic" keyword

picotalk 0.0.24
Simple voice call tool.
4 versions - Latest release: 5 months ago - 18 downloads last month - 5 stars on codeberg.org - 1 maintainer
hdl-registers 5.2.0
An open-source HDL register interface code generator fast enough to run in real time
17 versions - Latest release: 9 days ago - 1 dependent package - 1 dependent repositories - 912 downloads last month - 21 stars on GitHub - 1 maintainer
pyasic 0.57.0
A simplified and standardized interface for Bitcoin ASICs.
292 versions - Latest release: about 12 hours ago - 1 dependent repositories - 5.11 thousand downloads last month - 54 stars on GitHub - 1 maintainer
lctime 0.0.24
CMOS standard-cell characterization kit.
9 versions - Latest release: about 1 month ago - 1 dependent repositories - 83 downloads last month - 1 stars on codeberg.org - 1 maintainer
corsair 1.0.4
Control and Status Register map generator for FPGA/ASIC projects
8 versions - Latest release: about 1 year ago - 1 dependent repositories - 300 downloads last month - 89 stars on GitHub - 1 maintainer
lclayout 0.0.18
CMOS standard-cell layout generator.
3 versions - Latest release: 4 months ago - 1 dependent repositories - 28 downloads last month - 9,792 stars on GitHub - 1 maintainer
tsfpga 12.3.3
A flexible and scalable development platform for modern FPGA projects
30 versions - Latest release: 2 days ago - 1 dependent package - 1 dependent repositories - 1.07 thousand downloads last month - 7 stars on GitHub - 1 maintainer
librecell-common 0.0.16
Common utility functions for LibreCell suite.
10 versions - Latest release: about 1 month ago - 3 dependent packages - 3 dependent repositories - 90 downloads last month - 4 stars on codeberg.org - 1 maintainer
librecell-layout 0.0.23
DEPRECATED - use `lclayout` package instead - CMOS standard-cell layout generator.
9 versions - Latest release: about 1 month ago - 1 dependent package - 2 dependent repositories - 176 downloads last month - 0 stars on codeberg.org - 1 maintainer
librecell-lib 0.0.23
DEPRECATED - use `lctime` - CMOS standard-cell characterization kit.
12 versions - Latest release: about 1 month ago - 1 dependent package - 2 dependent repositories - 251 downloads last month - 1 stars on codeberg.org - 1 maintainer
librecell 0.0.23
DEPRECATED - use `lctime` and `lclayout` packages - CMOS layout generator and characterization.
10 versions - Latest release: about 1 month ago - 1 dependent repositories - 181 downloads last month - 4 stars on codeberg.org - 1 maintainer
Top 3.2% on pypi.org
vunit-hdl 4.7.0
VUnit is an open source unit testing framework for VHDL/SystemVerilog.
87 versions - Latest release: about 1 year ago - 4 dependent packages - 19 dependent repositories - 9.54 thousand downloads last month - 684 stars on GitHub - 2 maintainers
Top 3.8% on pypi.org
systemrdl-compiler 1.27.3
Parse and elaborate front-end for SystemRDL 2.0
46 versions - Latest release: 4 months ago - 10 dependent packages - 15 dependent repositories - 27 thousand downloads last month - 222 stars on GitHub - 1 maintainer
skillbridge 1.7.2
A seamless Python remote bridge to Cadence's Skill in Virtuoso
48 versions - Latest release: 22 days ago - 1 dependent package - 1 dependent repositories - 827 downloads last month - 159 stars on GitHub - 1 maintainer
Top 7.7% on pypi.org
peakrdl-uvm 2.3.0
Generate UVM register model from compiled SystemRDL input
9 versions - Latest release: about 1 year ago - 2 dependent packages - 4 dependent repositories - 6.63 thousand downloads last month - 45 stars on GitHub - 1 maintainer
Top 7.0% on pypi.org
peakrdl-ipxact 3.4.4
Import and export IP-XACT XML to/from the systemrdl-compiler register model
17 versions - Latest release: about 2 months ago - 4 dependent packages - 6 dependent repositories - 4.36 thousand downloads last month - 31 stars on GitHub - 1 maintainer
Top 9.7% on pypi.org
peakrdl 1.1.0
Command-line tool for control/status register automation and code generation.
11 versions - Latest release: 7 months ago - 3 dependent packages - 2 dependent repositories - 6.08 thousand downloads last month - 67 stars on GitHub - 1 maintainer
openlane 2.0.5
An infrastructure for implementing chip design flows
83 versions - Latest release: 2 days ago - 1 dependent package - 1 dependent repositories - 1.19 thousand downloads last month - 1,176 stars on GitHub - 2 maintainers
enerbitdso 0.1.8
enerBit DSO (Distribution System Operator) API client
5 versions - Latest release: 3 months ago - 111 downloads last month - 0 stars on GitHub - 2 maintainers
anyv-registers 0.1.0
A template-based hardware register bank generator
1 version - Latest release: 3 months ago - 8 downloads last month - 0 stars on GitHub - 1 maintainer
asic 0.2.5
Download and format ASIC files
21 versions - Latest release: 4 months ago - 160 downloads last month - 6 stars on GitHub - 2 maintainers
sky130-pdk 0.0.0
Python API for decoding information about Google's open source process design kit (PDK) for SkyWa...
1 version - Latest release: almost 2 years ago - 30 downloads last month - 2,843 stars on GitHub - 2 maintainers
gf180mcu-pdk 0.0.0
Python API for decoding information about Google's open source process design kit (PDK) for Globa...
1 version - Latest release: almost 2 years ago - 17 downloads last month - 340 stars on GitHub - 2 maintainers
gctime 0.0.17
CMOS standard-cell characterization kit.
1 version - Latest release: about 2 years ago - 1 dependent repositories - 9 downloads last month - 0 stars on codeberg.org - 1 maintainer
mera 1.6.0
An heterogeneous deep learning compiler framework.
10 versions - Latest release: 5 months ago - 1 dependent repositories - 80 downloads last month - 25 stars on GitHub - 1 maintainer
whatsminer 0.1.2
Unofficial python API for MicroBT Whatsminer ASICs
3 versions - Latest release: over 2 years ago - 1 dependent repositories - 200 downloads last month - 28 stars on GitHub - 1 maintainer
rodlayout 0.1.5
A python wrapper for the Skill objects in virtuoso
6 versions - Latest release: over 4 years ago - 1 dependent repositories - 20 downloads last month - 5 stars on GitHub - 1 maintainer
ralbot-uvm 1.2.0
Generate UVM register model from compiled SystemRDL input
4 versions - Latest release: over 3 years ago - 1 dependent repositories - 36 downloads last month - 45 stars on GitHub - 2 maintainers
hectare 0.2.4
VHDL generator from SystemRDL
4 versions - Latest release: almost 3 years ago - 1 dependent repositories - 37 downloads last month - 179 stars on GitHub - 1 maintainer
ralbot-html 1.7.1 removed
HTML documentation generator for SystemRDL-based register models
10 versions - Latest release: over 3 years ago - 30 stars on GitHub
Top 7.2% on pypi.org
peakrdl-html 2.10.1
HTML documentation generator for SystemRDL-based register models
17 versions - Latest release: 12 months ago - 1 dependent package - 4 dependent repositories - 12.3 thousand downloads last month - 43 stars on GitHub - 1 maintainer
open-source-pdks 0.0.0
Python API for decoding information about Google's open source process design kits (PDKs).
1 version - Latest release: almost 2 years ago - 16 downloads last month - 81 stars on GitHub - 2 maintainers
Top 7.7% on pypi.org
peakrdl-regblock 0.22.0
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
22 versions - Latest release: about 2 months ago - 1 dependent package - 3 dependent repositories - 8.45 thousand downloads last month - 46 stars on GitHub - 1 maintainer
pygears 0.3.4
Framework for functional hardware design approach
10 versions - Latest release: about 2 years ago - 5 dependent repositories - 93 downloads last month - 142 stars on GitHub - 1 maintainer
libsv 0.2.1
An open source, parameterized SystemVerilog hardware IP library
2 versions - Latest release: over 2 years ago - 1 dependent repositories - 17 downloads last month - 19 stars on GitHub - 1 maintainer
ralbot-ipxact 1.4.0 removed
Import and export IP-XACT XML to/from the systemrdl-compiler register model
7 versions - Latest release: over 3 years ago - 21 stars on GitHub
Related Keywords
fpga 18 eda 14 python 12 generator 10 vlsi 9 registers 9 cmos 8 cell 8 systemrdl-compiler 8 characterization 7 verilog 6 spice 5 systemverilog 5 liberty 5 hardware 5 design-automation 5 register-descriptions 5 digital 4 vhdl 4 gds 4 csr 4 stdcell 4 uvm 4 openroad 4 pdk 3 layout 3 klayout 3 skywater 3 systemrdl 3 uvm-register-model 3 PeakRDL 3 ASIC 3 CSR 3 compiler 3 FPGA 3 SystemVerilog 3 tool 3 Verilog 3 html 3 rtl 3 axi 3 cadence 2 gf180mcu 2 globalfoundries 2 bitcoin 2 180nm 2 hardware-description-language 2 asic-library 2 register abstraction layer 2 documentation 2 documentation-generator 2 virtuoso 2 systemverilog-hdl 2 whatsminer 2 ipxact 2 uvm-ral-model 2 api 2 xm 2 130nm 2 colombia 2 hdl 2 magic 2 SystemRDL 2 openram 2 register 2 ip-xact 2 expertos 1 integration 1 ip 1 development 1 ftp 1 mem 1 jinja2 1 microelectronics 1 semiconductor 1 client 1 power 1 operator 1 system 1 distribution 1 enerbit 1 yosys 1 antminer 1 hardware-libraries 1 hardware-designs 1 fpga-library 1 digital-design 1 Cocotb 1 IP 1 Hardware 1 Gears 1 HDL 1 simulator 1 Python 1 design 1 functional 1 sky130 1 silicon 1 jspec 1 microbt 1