pypi.org "systemverilog" keyword
View the packages on the pypi.org package registry that are tagged with the "systemverilog" keyword.
sv2svg 0.11.2
SystemVerilog to SVG using Schemdraw (left-to-right logic diagrams)17 versions - Latest release: about 15 hours ago - 1.47 thousand downloads last month - 1 stars on GitHub
Top 9.7% on pypi.org
16 versions - Latest release: about 18 hours ago - 3 dependent packages - 2 dependent repositories - 80 thousand downloads last month - 145 stars on GitHub - 1 maintainer
peakrdl 1.5.0
Toolchain for control/status register automation and code generation.16 versions - Latest release: about 18 hours ago - 3 dependent packages - 2 dependent repositories - 80 thousand downloads last month - 145 stars on GitHub - 1 maintainer
peakrdl-cli 1.5.0
Command-line tool for control/status register automation and code generation.5 versions - Latest release: about 18 hours ago - 28 thousand downloads last month - 145 stars on GitHub - 1 maintainer
pyslang 9.1.0
Python bindings for slang, a library for compiling SystemVerilog14 versions - Latest release: 7 days ago - 1 dependent package - 119 thousand downloads last month - 835 stars on GitHub - 1 maintainer
Top 7.3% on pypi.org
31 versions - Latest release: almost 2 years ago - 3 dependent repositories - 6.22 thousand downloads last month - 431 stars on GitHub - 2 maintainers
pymtl3 3.1.16
PyMTL 3 (Mamba): A Python-based hardware generation, simulation, and verification framework31 versions - Latest release: almost 2 years ago - 3 dependent repositories - 6.22 thousand downloads last month - 431 stars on GitHub - 2 maintainers
packtype 2.1.0
Packed data structure specifications for multi-language hardware projects9 versions - Latest release: 3 months ago - 1 dependent repositories - 98 downloads last month - 11 stars on GitHub - 1 maintainer
tsfpga 13.3.0
A flexible and scalable development platform for modern FPGA projects44 versions - Latest release: 3 months ago - 1 dependent package - 1 dependent repositories - 3.71 thousand downloads last month - 32 stars on GitHub - 1 maintainer
antlr4-verilog 4.0.0
Generated files from ANTLR4 for Verilog parsing4 versions - Latest release: about 3 years ago - 1 dependent repositories - 1.38 thousand downloads last month - 12 stars on GitHub - 1 maintainer
cocotbext-ahb 0.4.9
CocotbExt AHB Bus VIP41 versions - Latest release: 8 months ago - 662 downloads last month - 15 stars on GitHub - 1 maintainer
svreal 0.2.7
Library for working with fixed-point numbers in SystemVerilog26 versions - Latest release: almost 5 years ago - 2 dependent repositories - 770 downloads last month - 45 stars on GitHub - 1 maintainer
hdlconv 0.3.0
HDL converter, based on GHDL, Yosys, and the plugins ghdl-yosys-plugin and yosys-slang4 versions - Latest release: 7 months ago - 27 downloads last month - 25 stars on GitHub - 1 maintainer
forastero 1.2.1
cocotb verification framework with the batteries included5 versions - Latest release: 4 months ago - 178 downloads last month - 1 maintainer
hdlconvertor 2.3
VHDL and System Verilog parser written in c++19 versions - Latest release: over 4 years ago - 1 dependent package - 1 dependent repositories - 447 downloads last month - 302 stars on GitHub - 1 maintainer
Top 7.7% on pypi.org
26 versions - Latest release: 3 months ago - 1 dependent package - 3 dependent repositories - 67.3 thousand downloads last month - 71 stars on GitHub - 1 maintainer
peakrdl-regblock 1.1.1
Compile SystemRDL into a SystemVerilog control/status register (CSR) block26 versions - Latest release: 3 months ago - 1 dependent package - 3 dependent repositories - 67.3 thousand downloads last month - 71 stars on GitHub - 1 maintainer
jtag-axi 0.1.5
JTAG to AXI bridge python I/F6 versions - Latest release: about 1 month ago - 156 downloads last month - 2 stars on GitHub - 1 maintainer
svinst 0.1.9
Python library for parsing module definitions and instantiations from SystemVerilog files37 versions - Latest release: over 4 years ago - 1 dependent repositories - 145 downloads last month - 39 stars on GitHub - 1 maintainer
svdata 0.0.16
Parse systemverilog files in Python.16 versions - Latest release: 11 months ago - 402 downloads last month - 0 stars on GitHub - 1 maintainer
hdl-checker 0.7.4
HDL code checker19 versions - Latest release: about 4 years ago - 2 dependent repositories - 285 downloads last month - 185 stars on GitHub - 1 maintainer
ipsocgen 0.1.39
Generic SoC builder in HDL42 versions - Latest release: over 2 years ago - 53 downloads last month - 1 maintainer
cosa 0.3.1
CoreIR Symbolic Analyzer14 versions - Latest release: over 6 years ago - 5 dependent repositories - 250 downloads last month - 74 stars on GitHub - 2 maintainers
libsv 0.2.1
An open source, parameterized SystemVerilog hardware IP library2 versions - Latest release: over 3 years ago - 1 dependent repositories - 11 downloads last month - 29 stars on GitHub - 1 maintainer
pyralgen 1.0.1
Python based UVM-RAL generator1 version - Latest release: 3 months ago - 12 downloads last month - 0 stars on GitHub - 1 maintainer
erroranalyzer 2.2.1
ErrorAnalyzer is the EDA tool of choice to understand and find simulation failures faster3 versions - Latest release: almost 4 years ago - 1 dependent repositories - 14 downloads last month - 11 stars on GitHub - 1 maintainer
svut 1.10.0 💰
SystemVerilog Unit Test (SVUT)6 versions - Latest release: 12 months ago - 35 downloads last month - 80 stars on GitHub - 1 maintainer
pytcl-eda 0.3.0
PyTCL allows control EDA tools directly from Python that use TCL5 versions - Latest release: about 2 months ago - 22 downloads last month - 1 stars on gitlab.com - 1 maintainer
pip-hdl 0.3.0
Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Pyth...3 versions - Latest release: over 1 year ago - 12 downloads last month - 8 stars on GitHub - 1 maintainer
svmodule 1.2.0
[System]Verilog Module I/O parser and printer6 versions - Latest release: about 4 years ago - 1 dependent repositories - 52 downloads last month - 25 stars on GitHub - 1 maintainer
Top 9.5% on pypi.org
33 versions - Latest release: over 4 years ago - 7 dependent repositories - 144 downloads last month - 213 stars on GitHub - 1 maintainer
hwt 3.8
hdl synthesis toolkit33 versions - Latest release: over 4 years ago - 7 dependent repositories - 144 downloads last month - 213 stars on GitHub - 1 maintainer
cocotbext-waves 0.1.9
CocotbExt Wavedrom diagram generator9 versions - Latest release: 11 months ago - 143 downloads last month - 1 maintainer
pyrilog 0.2.4
A Python-based SystemVerilog code generator using context managers7 versions - Latest release: 24 days ago - 265 downloads last month - 1 maintainer
playhdl 0.2.1
Tool to play with HDL (inspired by EdaPlayground)3 versions - Latest release: almost 3 years ago - 10 downloads last month - 4 stars on GitHub - 1 maintainer
tree-sitter-systemverilog 0.2.1 💰
SystemVerilog 1800-2023 Parser3 versions - Latest release: 3 months ago - 292 downloads last month - 30 stars on GitHub - 1 maintainer
mavsec 1.0.0
A tool for the creation of JasperGold SVP principle tcl files.6 versions - Latest release: over 1 year ago - 21 downloads last month - 1 stars on GitHub - 1 maintainer
verilator 5.38.0
Python wrapping/binding for verilator8 versions - Latest release: 3 months ago - 1 dependent repositories - 1.95 thousand downloads last month - 3 stars on GitHub - 1 maintainer
ipxact2systemverilog 1.0.27
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description29 versions - Latest release: about 1 month ago - 1 dependent repositories - 237 downloads last month - 63 stars on GitHub - 1 maintainer
hdlconvertorast 1.2
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities12 versions - Latest release: almost 2 years ago - 1 dependent repositories - 8.95 thousand downloads last month - 37 stars on GitHub - 1 maintainer
sphinx-verilog-domain 0.0.2
Verilog Domain for Sphinx3 versions - Latest release: about 5 years ago - 10 dependent repositories - 23 downloads last month - 25 stars on GitHub - 2 maintainers
Top 3.5% on pypi.org
28 versions - Latest release: 10 days ago - 4 dependent packages - 16 dependent repositories - 98.6 thousand downloads last month - 715 stars on GitHub - 1 maintainer
edalize 0.6.2
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common ...28 versions - Latest release: 10 days ago - 4 dependent packages - 16 dependent repositories - 98.6 thousand downloads last month - 715 stars on GitHub - 1 maintainer
hdlconvertor-binary 2.3
VHDL and System Verilog parser written in c++1 version - Latest release: over 1 year ago - 63 downloads last month - 302 stars on GitHub - 1 maintainer
pytest-cocotb 0.1.0
Pytest plugin to integrate Cocotb1 version - Latest release: 7 months ago - 24 downloads last month - 1 stars on gitlab.com - 1 maintainer
blockwork 1.0
An opionated EDA flow1 version - Latest release: about 2 years ago - 13 downloads last month - 19 stars on GitHub - 1 maintainer
pynqpandas 0.0.1
Hardware-accelerated Pandas1 version - Latest release: almost 8 years ago - 1 dependent repositories - 5 downloads last month - 0 stars on GitHub - 1 maintainer
recover 0.0.0
An effective Remote Co-Verification (ReCoVer) library of hardware and software co-designs1 version - Latest release: almost 6 years ago - 2 dependent repositories - 21 downloads last month - 0 stars on gitlab.com - 1 maintainer
hectare 0.2.4
VHDL generator from SystemRDL4 versions - Latest release: over 4 years ago - 1 dependent repositories - 16 downloads last month - 198 stars on GitHub - 1 maintainer
jtag-to-axi
JTAG to AXI IP python I/F1 version - 2 stars on GitHub
hgdb-rtl 0.0.1
Creating HGDB symbol table from RTL1 version - Latest release: almost 3 years ago - 21 downloads last month - 726 stars on GitHub - 1 maintainer
socx-cli 0.3.0
System on chip verification and tooling infrastructure.13 versions - Latest release: 7 months ago - 47 downloads last month - 1 stars on GitHub - 1 maintainer
Related Keywords
verilog
37
hdl
20
fpga
17
python
16
vhdl
14
eda
11
rtl
10
asic
9
SystemVerilog
9
verilator
6
hardware
6
uvm
6
Verilog
6
compiler
6
parser
6
FPGA
6
verification
5
soc
5
vip
5
modelsim
5
VHDL
5
ASIC
5
simulation
4
parsing
4
xilinx
4
python3
4
vcs
4
icarus-verilog
4
systemrdl-compiler
4
vivado
4
antlr4
4
registers
4
system verilog
4
axi
4
tool
4
systemrdl
3
preprocessor
3
synthesis
3
ghdl
3
cocotb
3
xcelium
3
simulator
3
register abstraction layer
3
register-descriptions
3
flow
3
SystemRDL
3
parse
3
PeakRDL
3
generator
3
csr
3
CSR
3
HDL
2
EDA
2
software
2
codegen
2
codegenerator
2
synopsys
2
system-verilog
2
formal-verification
2
header
2
C
2
Xilinx
2
yosys
2
antrl4
2
systemverilog-parser
2
verilog-parser
2
vhdl-parser
2
jtag
2
testing
2
altera
2
test
2
language-service
2
cadence
2
systemc
2
slang
2
uvm-register-model
2
Cocotb
2
questa
2
hardware-description-language
2
command-line-tool
2
apb
2
amba
2
siemens
2
hardware-verification
2
pip
1
ip-core
1
incremental
1
tree-sitter
1
code-generation
1
wavedrom
1
rtl-design
1
editor
1
hls
1
hcl
1
surfer
1
svut
1
Xcelium
1
Vivado
1
Cadence
1
tcl
1