Ecosyste.ms: Packages

An open API service providing package, version and dependency metadata of many open source software ecosystems and registries.

pypi.org "systemverilog" keyword

Top 9.5% on pypi.org
hwt 3.8
hdl synthesis toolkit
33 versions - Latest release: almost 3 years ago - 7 dependent repositories - 211 downloads last month - 188 stars on GitHub - 1 maintainer
tsfpga 12.3.3
A flexible and scalable development platform for modern FPGA projects
30 versions - Latest release: 2 days ago - 1 dependent package - 1 dependent repositories - 1.07 thousand downloads last month - 7 stars on GitHub - 1 maintainer
blockwork 1.0
An opionated EDA flow
1 version - Latest release: 10 months ago - 22 downloads last month - 12 stars on GitHub - 1 maintainer
pyslang 5.0.0
Python bindings for slang, a library for compiling SystemVerilog
8 versions - Latest release: 5 months ago - 1 dependent package - 1.49 thousand downloads last month - 540 stars on GitHub - 1 maintainer
Top 9.7% on pypi.org
peakrdl 1.1.0
Command-line tool for control/status register automation and code generation.
11 versions - Latest release: 7 months ago - 3 dependent packages - 2 dependent repositories - 6.08 thousand downloads last month - 67 stars on GitHub - 1 maintainer
hdlconvertor 2.3
VHDL and System Verilog parser written in c++
19 versions - Latest release: almost 3 years ago - 1 dependent package - 1 dependent repositories - 167 downloads last month - 265 stars on GitHub - 1 maintainer
hdlconvertor-binary 2.3
VHDL and System Verilog parser written in c++
1 version - Latest release: 4 months ago - 112 downloads last month - 265 stars on GitHub - 1 maintainer
hdlconvertorast 1.2
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities
12 versions - Latest release: 7 months ago - 1 dependent repositories - 1.02 thousand downloads last month - 26 stars on GitHub - 1 maintainer
Top 3.5% on pypi.org
edalize 0.5.4
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common ...
25 versions - Latest release: 5 months ago - 4 dependent packages - 16 dependent repositories - 3.76 thousand downloads last month - 587 stars on GitHub - 1 maintainer
pip-hdl 0.3.0
Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Pyth...
3 versions - Latest release: 4 months ago - 27 downloads last month - 4 stars on GitHub - 1 maintainer
cocotbext-ahb 0.2.6
CocotbExt AHB Bus VIP
19 versions - Latest release: 5 months ago - 148 downloads last month - 5 stars on GitHub - 1 maintainer
Top 7.3% on pypi.org
pymtl3 3.1.16
PyMTL 3 (Mamba): A Python-based hardware generation, simulation, and verification framework
31 versions - Latest release: 7 months ago - 3 dependent repositories - 761 downloads last month - 351 stars on GitHub - 2 maintainers
hgdb-rtl 0.0.1
Creating HGDB symbol table from RTL
1 version - Latest release: over 1 year ago - 10 downloads last month - 536 stars on GitHub - 1 maintainer
svreal 0.2.7
Library for working with fixed-point numbers in SystemVerilog
26 versions - Latest release: over 3 years ago - 2 dependent repositories - 88 downloads last month - 40 stars on GitHub - 1 maintainer
svmodule 1.2.0
[System]Verilog Module I/O parser and printer
6 versions - Latest release: almost 3 years ago - 1 dependent repositories - 59 downloads last month - 22 stars on GitHub - 1 maintainer
sphinx-verilog-domain 0.0.2
Verilog Domain for Sphinx
3 versions - Latest release: over 3 years ago - 10 dependent repositories - 225 downloads last month - 21 stars on GitHub - 2 maintainers
recover 0.0.0
An effective Remote Co-Verification (ReCoVer) library of hardware and software co-designs
1 version - Latest release: over 4 years ago - 2 dependent repositories - 17 downloads last month - 0 stars on GitLab.com - 1 maintainer
pynqpandas 0.0.1
Hardware-accelerated Pandas
1 version - Latest release: over 6 years ago - 1 dependent repositories - 7 downloads last month - 0 stars on GitHub - 1 maintainer
packtype 1.1.5
Packed data structure specifications for multi-language hardware projects
8 versions - Latest release: over 2 years ago - 1 dependent repositories - 69 downloads last month - 3 stars on GitHub - 1 maintainer
ipxact2systemverilog 1.0.23
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description
25 versions - Latest release: 6 months ago - 1 dependent repositories - 80 downloads last month - 55 stars on GitHub - 1 maintainer
hectare 0.2.4
VHDL generator from SystemRDL
4 versions - Latest release: almost 3 years ago - 1 dependent repositories - 37 downloads last month - 179 stars on GitHub - 1 maintainer
erroranalyzer 2.2.1
ErrorAnalyzer is the EDA tool of choice to understand and find simulation failures faster
3 versions - Latest release: over 2 years ago - 1 dependent repositories - 28 downloads last month - 10 stars on GitHub - 1 maintainer
cosa 0.3.1
CoreIR Symbolic Analyzer
14 versions - Latest release: about 5 years ago - 5 dependent repositories - 48 downloads last month - 60 stars on GitHub - 2 maintainers
antlr4-verilog 4.0.0
Generated files from ANTLR4 for Verilog parsing
4 versions - Latest release: almost 2 years ago - 1 dependent repositories - 436 downloads last month - 9 stars on GitHub - 1 maintainer
svinst 0.1.9
Python library for parsing module definitions and instantiations from SystemVerilog files
37 versions - Latest release: about 3 years ago - 1 dependent repositories - 420 downloads last month - 39 stars on GitHub - 1 maintainer
playhdl 0.2.1
Tool to play with HDL (inspired by EdaPlayground)
3 versions - Latest release: over 1 year ago - 31 downloads last month - 4 stars on GitHub - 1 maintainer
Top 7.7% on pypi.org
peakrdl-regblock 0.22.0
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
22 versions - Latest release: about 2 months ago - 1 dependent package - 3 dependent repositories - 8.45 thousand downloads last month - 46 stars on GitHub - 1 maintainer
hdl-checker 0.7.4
HDL code checker
19 versions - Latest release: almost 3 years ago - 2 dependent repositories - 301 downloads last month - 176 stars on GitHub - 1 maintainer
ipsocgen 0.1.39
Generic SoC builder in HDL
42 versions - Latest release: 11 months ago - 273 downloads last month - 1 maintainer
svut 1.9.0 💰
SystemVerilog Unit Test (SVUT)
2 versions - Latest release: over 1 year ago - 42 downloads last month - 61 stars on GitHub - 1 maintainer
libsv 0.2.1
An open source, parameterized SystemVerilog hardware IP library
2 versions - Latest release: over 2 years ago - 1 dependent repositories - 17 downloads last month - 19 stars on GitHub - 1 maintainer