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pypi.org "systemverilog" keyword

View the packages on the pypi.org package registry that are tagged with the "systemverilog" keyword.

hgdb-rtl 0.0.1
Creating HGDB symbol table from RTL
1 version - Latest release: over 2 years ago - 35 downloads last month - 726 stars on GitHub - 1 maintainer
pyslang 8.0.0
Python bindings for slang, a library for compiling SystemVerilog
11 versions - Latest release: 2 months ago - 1 dependent package - 55 thousand downloads last month - 726 stars on GitHub - 1 maintainer
hdl-checker 0.7.4
HDL code checker
19 versions - Latest release: over 3 years ago - 2 dependent repositories - 757 downloads last month - 185 stars on GitHub - 1 maintainer
Top 7.3% on pypi.org
pymtl3 3.1.16
PyMTL 3 (Mamba): A Python-based hardware generation, simulation, and verification framework
31 versions - Latest release: over 1 year ago - 3 dependent repositories - 1.2 thousand downloads last month - 409 stars on GitHub - 2 maintainers
svut 1.10.0 💰
SystemVerilog Unit Test (SVUT)
6 versions - Latest release: 6 months ago - 300 downloads last month - 77 stars on GitHub - 1 maintainer
Top 3.5% on pypi.org
edalize 0.6.1
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common ...
27 versions - Latest release: 6 days ago - 4 dependent packages - 16 dependent repositories - 9.91 thousand downloads last month - 675 stars on GitHub - 1 maintainer
pytest-cocotb 0.1.0
Pytest plugin to integrate Cocotb
1 version - Latest release: about 1 month ago - 202 downloads last month - 1 stars on gitlab.com - 1 maintainer
svdata 0.0.16
Parse systemverilog files in Python.
16 versions - Latest release: 6 months ago - 8.43 thousand downloads last month - 0 stars on GitHub - 1 maintainer
Top 9.7% on pypi.org
peakrdl 1.2.3
Toolchain for control/status register automation and code generation.
13 versions - Latest release: 4 months ago - 3 dependent packages - 2 dependent repositories - 52.5 thousand downloads last month - 123 stars on GitHub - 1 maintainer
peakrdl-cli 1.2.3
Command-line tool for control/status register automation and code generation.
2 versions - Latest release: 4 months ago - 32.3 thousand downloads last month - 123 stars on GitHub - 1 maintainer
svinst 0.1.9
Python library for parsing module definitions and instantiations from SystemVerilog files
37 versions - Latest release: almost 4 years ago - 1 dependent repositories - 1.6 thousand downloads last month - 39 stars on GitHub - 1 maintainer
antlr4-verilog 4.0.0
Generated files from ANTLR4 for Verilog parsing
4 versions - Latest release: almost 3 years ago - 1 dependent repositories - 1.38 thousand downloads last month - 12 stars on GitHub - 1 maintainer
packtype 1.1.5
Packed data structure specifications for multi-language hardware projects
8 versions - Latest release: over 3 years ago - 1 dependent repositories - 407 downloads last month - 3 stars on GitHub - 1 maintainer
blockwork 1.0
An opionated EDA flow
1 version - Latest release: over 1 year ago - 68 downloads last month - 17 stars on GitHub - 1 maintainer
pip-hdl 0.3.0
Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Pyth...
3 versions - Latest release: about 1 year ago - 154 downloads last month - 4 stars on GitHub - 1 maintainer
hdlconvertor 2.3
VHDL and System Verilog parser written in c++
19 versions - Latest release: almost 4 years ago - 1 dependent package - 1 dependent repositories - 461 downloads last month - 289 stars on GitHub - 1 maintainer
hdlconvertor-binary 2.3
VHDL and System Verilog parser written in c++
1 version - Latest release: over 1 year ago - 204 downloads last month - 289 stars on GitHub - 1 maintainer
jtag-axi 0.1.4
JTAG to AXI bridge python I/F
5 versions - Latest release: 7 months ago - 176 downloads last month - 1 maintainer
erroranalyzer 2.2.1
ErrorAnalyzer is the EDA tool of choice to understand and find simulation failures faster
3 versions - Latest release: over 3 years ago - 1 dependent repositories - 134 downloads last month - 10 stars on GitHub - 1 maintainer
verilator 5.32.0
Python wrapping/binding for verilator
6 versions - Latest release: 4 months ago - 1 dependent repositories - 881 downloads last month - 0 stars on GitHub - 1 maintainer
Top 7.7% on pypi.org
peakrdl-regblock 1.0.0
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
24 versions - Latest release: 9 days ago - 1 dependent package - 3 dependent repositories - 52.4 thousand downloads last month - 60 stars on GitHub - 1 maintainer
pytcl-eda 0.2.1
PyTCL allows control EDA tools directly from Python that use TCL
4 versions - Latest release: about 1 month ago - 573 downloads last month - 1 stars on gitlab.com - 1 maintainer
svreal 0.2.7
Library for working with fixed-point numbers in SystemVerilog
26 versions - Latest release: over 4 years ago - 2 dependent repositories - 470 downloads last month - 44 stars on GitHub - 1 maintainer
ipxact2systemverilog 1.0.23
Generate VHDL, SystemVerilog, html, rst, md, pdf, c headers from an IPXACT description
25 versions - Latest release: over 1 year ago - 1 dependent repositories - 379 downloads last month - 57 stars on GitHub - 1 maintainer
hdlconvertorast 1.2
A library of AST nodes for HDL languages (Verilog, VHDL, ...) and transpiler/compiler utilities
12 versions - Latest release: over 1 year ago - 1 dependent repositories - 943 downloads last month - 31 stars on GitHub - 1 maintainer
Top 9.5% on pypi.org
hwt 3.8
hdl synthesis toolkit
33 versions - Latest release: almost 4 years ago - 7 dependent repositories - 762 downloads last month - 209 stars on GitHub - 1 maintainer
cocotbext-waves 0.1.9
CocotbExt Wavedrom diagram generator
9 versions - Latest release: 6 months ago - 320 downloads last month - 1 maintainer
pynqpandas 0.0.1
Hardware-accelerated Pandas
1 version - Latest release: over 7 years ago - 1 dependent repositories - 30 downloads last month - 0 stars on GitHub - 1 maintainer
hdlconv 0.3.0
HDL converter, based on GHDL, Yosys, and the plugins ghdl-yosys-plugin and yosys-slang
4 versions - Latest release: about 2 months ago - 294 downloads last month - 23 stars on GitHub - 1 maintainer
sphinx-verilog-domain 0.0.2
Verilog Domain for Sphinx
3 versions - Latest release: over 4 years ago - 10 dependent repositories - 315 downloads last month - 23 stars on GitHub - 2 maintainers
tsfpga 13.2.0
A flexible and scalable development platform for modern FPGA projects
40 versions - Latest release: about 1 month ago - 1 dependent package - 1 dependent repositories - 1.79 thousand downloads last month - 23 stars on GitHub - 1 maintainer
socx-cli 0.3.0
System on chip verification and tooling infrastructure.
13 versions - Latest release: about 1 month ago - 1.47 thousand downloads last month - 1 stars on GitHub - 1 maintainer
hectare 0.2.4
VHDL generator from SystemRDL
4 versions - Latest release: almost 4 years ago - 1 dependent repositories - 155 downloads last month - 198 stars on GitHub - 1 maintainer
cosa 0.3.1
CoreIR Symbolic Analyzer
14 versions - Latest release: about 6 years ago - 5 dependent repositories - 339 downloads last month - 60 stars on GitHub - 2 maintainers
cocotbext-ahb 0.4.9
CocotbExt AHB Bus VIP
41 versions - Latest release: 3 months ago - 1.14 thousand downloads last month - 13 stars on GitHub - 1 maintainer
svmodule 1.2.0
[System]Verilog Module I/O parser and printer
6 versions - Latest release: over 3 years ago - 1 dependent repositories - 320 downloads last month - 25 stars on GitHub - 1 maintainer
recover 0.0.0
An effective Remote Co-Verification (ReCoVer) library of hardware and software co-designs
1 version - Latest release: over 5 years ago - 2 dependent repositories - 40 downloads last month - 0 stars on gitlab.com - 1 maintainer
forastero 1.0
cocotb verification framework with the batteries included
1 version - Latest release: 7 months ago - 80 downloads last month - 1 maintainer
playhdl 0.2.1
Tool to play with HDL (inspired by EdaPlayground)
3 versions - Latest release: over 2 years ago - 134 downloads last month - 4 stars on GitHub - 1 maintainer
ipsocgen 0.1.39
Generic SoC builder in HDL
42 versions - Latest release: almost 2 years ago - 406 downloads last month - 1 maintainer
libsv 0.2.1
An open source, parameterized SystemVerilog hardware IP library
2 versions - Latest release: about 3 years ago - 1 dependent repositories - 89 downloads last month - 26 stars on GitHub - 1 maintainer
jtag-to-axi removed
JTAG to AXI IP python I/F
1 version