Ecosyste.ms: Packages
An open API service providing package, version and dependency metadata of many open source software ecosystems and registries.
pypi.org "verilator" keyword
Top 3.5% on pypi.org
25 versions - Latest release: 5 months ago - 4 dependent packages - 16 dependent repositories - 3.76 thousand downloads last month - 587 stars on GitHub - 1 maintainer
edalize 0.5.4
Library for interfacing EDA tools such as simulators, linters or synthesis tools, using a common ...25 versions - Latest release: 5 months ago - 4 dependent packages - 16 dependent repositories - 3.76 thousand downloads last month - 587 stars on GitHub - 1 maintainer
verilator-mem-if 0.1.5
Useful backdoor memory access tools for Verilator simulations.6 versions - Latest release: over 1 year ago - 20 downloads last month - 0 stars on GitHub - 1 maintainer
svreal 0.2.7
Library for working with fixed-point numbers in SystemVerilog26 versions - Latest release: over 3 years ago - 2 dependent repositories - 88 downloads last month - 40 stars on GitHub - 1 maintainer
erroranalyzer 2.2.1
ErrorAnalyzer is the EDA tool of choice to understand and find simulation failures faster3 versions - Latest release: over 2 years ago - 1 dependent repositories - 28 downloads last month - 10 stars on GitHub - 1 maintainer
playhdl 0.2.1
Tool to play with HDL (inspired by EdaPlayground)3 versions - Latest release: over 1 year ago - 31 downloads last month - 4 stars on GitHub - 1 maintainer
svut 1.9.0 💰
SystemVerilog Unit Test (SVUT)2 versions - Latest release: over 1 year ago - 42 downloads last month - 61 stars on GitHub - 1 maintainer
Related Keywords
systemverilog
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verilog
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simulation
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icarus-verilog
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hdl
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eda
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modelsim
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synthesis
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vivado
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vcs
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fpga
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verification
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uvm
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testbench
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xrun
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xcelium
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ncsim
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iverilog
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irun
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icarus
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VHDL
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testing
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flow
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foss
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gtkwave
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mit-license
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python
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simulator
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svut
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tdd
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tdd-utilities
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testcase
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vcd
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verification-methodologies
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EDA
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rtl
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FPGA
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altera
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fossi
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ghdl
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icestorm
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lattice
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riviera-pro
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spyglass
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vhdl
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xilinx
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yosys
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opentitan
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backdoor
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fixed-point
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fixed point
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system-verilog
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system verilog
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synthesizable
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floating-point
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