Ecosyste.ms: Packages

FPGA 20 Verilog 14 SystemVerilog 11 RTL 10 HDL 9 verilog 9 hdl 9 simulation 9 vhdl 7 Xilinx 7 rtl 7 Altera 6 synthesis 6 fpga 5 eda 4 EDA 4 python 4 verification 4 Synthesis 4 Python 4 ASIC 3 systemverilog 3 hardware 3 Hardware Design 2 Hierarchical Register Description 2 modelsim 2 xilinx 2 Firmware Generation 2 Electronic Systems 2 Electronic Design Automation 2 Documentation Generation 2 Co-simulation 2 Control and Status Registers 2 Bus Interface 2 UVM 2 DV 2 Python3 2 system 2 testbench 2 circuit 2 Hardware 2 HLS 2 Software Generation 2 Register Synthesis 2 ghdl 2 Register Addressing 2 C 2 Memory 2 Simulation 1 xilinx-vivado 1 myhdl 1 OSVVM 1 GHDL 1 Questa 1 fusesoc 1 Vivado 1 TCL 1 Design Space 1 Genetic Algorithm 1 LightGBM 1 machine learning 1 traffic classification 1 liberouter 1 network-development-kit 1 vcd 1 fst 1 development 1 Electronic 1 Design 1 Automation 1 Tool 1 vivado-simulator 1 vim-ale 1 vim 1 syntax-checker 1 questasim 1 mentor-msim 1 lsp-server 1 language-server 1 hdl-checker 1 emacs-lsp 1 coc-nvim 1 vim-hdl 1 vimhdl 1 protocol 1 server 1 language 1 LSP 1 linter 1 cocotb 1 design 1 parser 1 test 1 IP 1 flow 1 automation 1 Verification 1 Simulator 1 crc32 1 crc-calculation 1